K4S281632F-LC60 Samsung Semiconductor, K4S281632F-LC60 Datasheet - Page 3

• Manufacturer Part Number: K4S281632F-LC60
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S281632F-LC60

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

SDRAM 128Mb F-die (x4, x8, x16)
8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
•
• RoHS compliant
GENERAL DESCRIPTION
8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
The K4S280432F / K4S280832F / K4S281632F is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x
54
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
TSOP(II)
K4S281632F-UC(L)60/75
K4S280432F-UC(L)75
K4S280832F-UC(L)75
Pb-free Package
Part No.
Organization
32Mx4
16Mx8
8Mx16
Row & Column address configuration
Orgainization
32M x 4
16M x 8
8M x 16
Row Address
A0~A11
A0~A11
A0~A11
Max Freq.
133MHz
133MHz
166MHz
Column Address
A0-A9, A11
A0-A9
A0-A8
Interface
LVTTL
LVTTL
LVTTL
Rev. 1.2 August 2004
CMOS SDRAM
54pin TSOP(II)
54pin TSOP(II)
54pin TSOP(II)
Package