K4D261638I-LC40 Samsung Semiconductor, K4D261638I-LC40 Datasheet
K4D261638I-LC40
Specifications of K4D261638I-LC40
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K4D261638I-LC40 Summary of contents
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... K4D261638I 128Mbit GDDR SDRAM Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4D261638I Revision History Revision Month Year 0.0 March 2005 0.1 May 2005 1.0 August 2005 1.1 January 2006 1.2 November 2006 - Target Spec - Defined target specification - Corrected typo. - Added CL2 feature in AC Characteristics. - Finalized SPEC - Deleted CL2.5 option - Corrected typo. - Corrected typo. ...
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... Differential clock input • Wrtie-Interrupted by Read Function 2.0 ORDERING INFORMATION Part NO. K4D261638I-LC40 K4D261638I-LC50 * K4D261638I-TC is the Leaded package part number. * For K4D261638I-LC50, VDD & VDDQ = 2.375V to 2.7V. 3.0 GENERAL DESCRIPTION FOR 2M x 16Bit x 4 Bank DDR SDRAM ...
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... K4D261638I 4.0 PIN CONFIGURATION PIN DESCRIPTION CK,CK Differential Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQS Data Strobe L(U)DM Data Mask RFU Reserved for Future Use (Top View DDQ SSQ 7 DQ ...
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... K4D261638I 5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type *1 Input CK, CK CKE Input CS Input RAS Input CAS Input WE Input LDQS,UDQS Input/Output LDM,UDM Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply REF No connection/ NC/RFU Reserved for future use *1 : The timing reference point for the differential clocking is the cross point of CK and CK. ...
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... K4D261638I 6.0 BLOCK DIAGRAM (2Mbit x 16I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 16 Intput Buffer CK, CK Data Input Register Serial to parallel 2Mx16 2Mx16 2Mx16 2Mx16 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register ...
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... K4D261638I 7.0 FUNCTIONAL DESCRIPTION 7.1 Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply V before DDQ - Apply V before V & V DDQ REF 2. Start clock and maintain stable condition for minimum 200us. ...
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... K4D261638I 7.2 MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different appli- cations ...
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... K4D261638I 7.3 EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. ...
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... K4D261638I 7.4 WRITE INTERRUPTED BY A READ A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM ...
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... IH DDQ 5. V (mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate For any pin under test input of 0V < For K4D261638I-LC50, V & 2.375V to 2.7V. DD DDQ 9.2 DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted ( TA=0 to 65°C) Parameter ...
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... Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Note : 1. In case of differential clocks(CK and CK ), input reference voltage for clock and CK’s crossing point For K4D261638I-LC50, V & = 2.375V to 2.7V. DDQ DD Output =0V, V =2.5V+ 5 Symbol Min ...
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... K4D261638I 9.5 CAPACITANCE Parameter Input capacitance( CK Input capacitance ~ Input capacitance( CKE, CS, RAS,CAS Data & DQS input/output capacitance(DQ Input capacitance(DM0 ~ DM3) DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Decoupling Capacitance between V DD Decoupling Capacitance between V DDQ 1. V and V pins are separated each other ...
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... K4D261638I AC CHARACTERISTICS (II)_Continued Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge @Normal Precharge Last data in to Row precharge @Auto Precharge Last data in to Read command Col ...
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... K4D261638I 10.0 SIMPLIFIED TIMING Simplified Timing @ BL CK, CK BA[1:0] BAa BAa A10/AP Ra ADDR Ra Ca (A0~A9 ,A11) WE DQS Da0 Da1 Da2 Da3 DQ DM COM ACT_A WR_A t RCD t RAS Normal Write Burst (@ BL= BAa PRECH ACT_A 128M GDDR SDRAM BAb BAa BAa BAb Da0 Da1 Da2 Da3 ...
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... K4D261638I 11.0 IBIS : I/V Characteristics for Input and Output Buffers (1) Full Strength Driver Characteristics Pulldown Current (mA) Voltage Minimum (V) 0.0 0 0.1 1.368 0.2 4.968 0.3 8.46 0.4 11.808 0.5 14.904 0.6 17.892 0.7 20.376 0.8 22.716 0.9 24.624 1.0 26.208 1.1 27.432 1 ...
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... K4D261638I 11.0 IBIS : I/V Characteristics for Input and Output Buffers (2) Weak Strength Driver Characteristics Pulldown Current (mA) Voltage Minimum (V) 0.0 0 0.1 1.332 0.2 4.752 0.3 7.992 0.4 11.008 0.5 13.968 0.6 16.74 0.7 19.08 0.8 21.24 0.9 23.04 1.0 24.516 1.1 25.596 1 ...
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... K4D261638I 11.0 IBIS : I/V Characteristics for Input and Output Buffers (3) Matched Strength Driver Characteristics Pulldown Current (mA) Voltage Minimum (V) 0.0 0 0.1 1.152 0.2 2.988 0.3 4.788 0.4 6.48 0.5 8.028 0.6 9.396 0.7 10.692 0.8 11.7 0.9 12.564 1.0 13.248 1.1 13.716 1 ...
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... K4D261638I 12.0 PACKAGE DIMENSIONS (66pin TSOP-II) #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10× 128M GDDR SDRAM Units : Millimeters (10×) (10×) +0.075 0.125 -0.035 0.10 MAX 0.25TYP [ ] 0.075 MAX 0×~8× ...