MT48LC16M4A2TG-7EL Micron Technology Inc, MT48LC16M4A2TG-7EL Datasheet - Page 35

• Manufacturer Part Number: MT48LC16M4A2TG-7EL
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M4A2TG-7EL

• Lead Free Status / RoHS Status: Not Compliant

Figure 26:
Clock Suspend
Burst Read/Single Write
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
Power-Down
COMMAND
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figures 27 and 28 on page 36.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
CKE
CLK
All banks idle
Enter power-down mode.
t CKS
NOP
Input buffers gated off
35
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Exit power-down mode.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
> t CKS
NOP
64Mb: x4, x8, x16 SDRAM
DON’T CARE
©2000 Micron Technology, Inc. All rights reserved.
ACTIVE
t RCD
t RAS
t RC
Commands