CY7C4251-10JC Cypress Semiconductor Corp, CY7C4251-10JC Datasheet - Page 12
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CY7C4251-10JC
Manufacturer Part Number
CY7C4251-10JC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C4251-10JC.pdf
(20 pages)
Specifications of CY7C4251-10JC
Configuration
Dual
Density
64Kb
Access Time (max)
8ns
Word Size
9b
Organization
8Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
35mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4251-10JCT
Manufacturer:
CYPR
Quantity:
4 321
Document #: 38-06016 Rev. *D
Notes
WEN2/LD
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. Holding WEN2/LD HIGH during reset makes the pin act as a second enable pin. Holding WEN2/LD LOW during reset makes the pin act as a load enable for the
18. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1.
19. When t
20. The first word is available the cycle after EF goes HIGH, always.
programmable flag offset registers.
t
SKEW1
Q
EF,PAE
FF,PAF,
REN1,
WEN1
0 -
REN2
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
RS
SKEW1
[17]
Q
(if applicable)
8
D
WEN2
Q
> minimum specification, t
WCLK
WEN1
REN1,
RCLK
REN2
0
0
–D
–Q
OE
EF
8
8
Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write
t
ENS
t
DS
D
0 (FIRST
FRL
(maximum) = t
VALID
t
t
t
t
RSF
RSF
RSF
SKEW1
t
Write)
RS
t
t
t
t
OLZ
t
RSS
RSS
RSS
FRL
CLK
Figure 7. Reset Timing
[19]
+ t
SKEW1
t
REF
D
1
. When t
t
SKEW1
OE
< minimum specification, t
t
A
D
[16]
2
[]
t
t
t
RSR
RSR
RSR
CY7C4421/4201/4211/4221
D
0
FRL
D
t
A
(maximum) = either 2*t
3
CY7C4231/4241/4251
D
OE = 0
OE = 1
1
D
4
CLK
[18]
+ t
Page 12 of 20
SKEW1
or t
CLK
+
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