M29W400FT55N3E Micron Technology Inc, M29W400FT55N3E Datasheet
M29W400FT55N3E
Specifications of M29W400FT55N3E
Related parts for M29W400FT55N3E
M29W400FT55N3E Summary of contents
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... Top device code M29W800FT: 22D7h; M29W400FT: 00EEh – Bottom device code M29W800FB: 225Bh; M29W400FB: 00EFh RoHS packages available July 2010 M29W800FT M29W400FT M29W800FB M29W400FB Boot Block 3 V Supply Flash memory TSOP48 (N) 12 × TFBGA48 (ZA Automotive device grade 3: Automotive device grade Rev 5 ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Erase timer bit (DQ3 5.5 Alternative toggle bit (DQ2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Appendix A Block address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Appendix B Common Flash interface (CFI Appendix C Block protection C.1 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 C.2 In-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3/56 ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description The M29W800FT/B and M29W400FT/B are 8-Mbit (1 Mbit × 512 Kbit × 16) and 4-Mbit (512 Kbit × 256 Kbit × 16) non-volatile memory devices that can be read, erased and reprogrammed. These operations ...
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Table 1. Signal names Signal name A0-A18 Address inputs DQ0-DQ7 Data inputs/outputs DQ8-DQ14 Data inputs/outputs DQ15A–1 Data input/output or address input E Chip Enable G Output Enable W Write Enable RP Reset/block temporary unprotect RB Ready/busy output BYTE Byte/word organization ...
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Figure 3. TSOP connections, 400FT/B 8/56 A15 1 48 A16 A14 BYTE A13 V SS A12 DQ15A–1 A11 DQ7 A10 DQ14 A9 DQ6 A8 DQ13 NC DQ5 NC DQ12 W DQ4 DQ11 ...
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Figure 4. BGA connections, 400FT A17 DQ0 DQ8 G G DQ9 DQ1 ...
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Figure 5. BGA connections, 800FT 10/ A17 A18 DQ0 DQ2 DQ5 DQ12 E ...
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Figure 6. Block addresses, 800FT/B(× 8) Top boot block addresses (x 8) FFFFFh 16 Kbyte FC000h FBFFFh 8 Kbyte FA000h F9FFFh 8 Kbyte F8000h F7FFFh 32 Kbyte F0000h EFFFFh 64 Kbyte E0000h 64 Kbyte blocks 1FFFFh 64 Kbyte 10000h 0FFFFh ...
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Figure 7. Block addresses, 800FT/B(× 16) Top boot block addresses (x 16) 7FFFFh 8 Kword 7E000h 7DFFFh 4 Kword 7D000h 7CFFFh 4 Kword 7C000h 7BFFFh 16 Kword 78000h 77FFFh 32 Kword 70000h 0FFFFh 32 Kword 08000h 07FFFh 32 Kword 00000h ...
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Figure 8. Block addresses, 400FT/B(× 8) Top boot block addresses (x 8) 7FFFFh 16 Kbyte 7C000h 7BFFFh 8 Kbyte 7A000h 79FFFh 8 Kbyte 78000h 77FFFh 32 Kbyte 70000h 6FFFFh 64 Kbyte 60000h 1FFFFh 64 Kbyte 10000h 0FFFFh 64 Kbyte 00000h ...
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Signal descriptions See Figure 1: Logic diagram connected to this device. 2.1 Address inputs (A0-A18) The address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands ...
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Write Enable (W) The Write Enable, W, controls the bus write operation of the memory’s command interface. 2.8 Reset/Block Temporary Unprotect (RP) The Reset/Block Temporary Unprotect pin can be used to apply a hardware reset to the memory or ...
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V supply voltage CC The V supply voltage supplies the power for all operations (read, program, erase etc.). CC The command interface is disabled when the V voltage This prevents bus write operations from accidentally damaging the ...
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Bus operations There are five standard bus operations that control the device. These are bus read, bus write, output disable, standby and automatic standby. See operations, for a summary. Typically glitches of less than Chip Enable ...
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Special bus operations Additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. These bus operations are intended for use by programming equipment and are not usually used in applications. ...
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Table 3. Bus operations, BYTE = V Operation E G Bus read Bus write Output disable X V Standby Read manufacturer code Read device code ...
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Command interface All bus write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus write operations. Failure to observe a valid sequence of bus write operations will result in the ...
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Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four bus write operations, the final write operation latches the address and data in ...
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Chip Erase command The Chip Erase command can be used to erase the entire chip. Six bus write operations are required to issue the Chip Erase command and start the program/erase controller. If any blocks are protected then these ...
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... An erase can be suspended and resumed more than once. 4.11 Read CFI Query command The Read CFI Query command is used to read data from the common Flash interface (CFI) memory area. This command is valid when the device is in the read array mode, or when the device is in auto select mode. ...
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Block Protect and Chip Unprotect commands Each block can be separately protected against accidental program or erase. The whole chip can be unprotected to allow the data inside the blocks to be changed. Block protect and chip unprotect operations ...
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Table 5. Commands, 8-bit mode, BYTE = V Command Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 X Read/Reset 3 AAA Auto Select 3 AAA Program 4 AAA Unlock Bypass 3 AAA Unlock Bypass 2 ...
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Table 7. Program, erase times and endurance cycles, 800F Parameter Chip erase Block erase (64 Kbytes) Erase suspend latency time Program (byte or word) Chip program (byte by byte) Chip program (word by word) Program/erase cycles (per block) Data retention ...
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Status register Bus read operations from any address always read the status register during program and erase operations also read during erase suspend when an address within a block being erased is accessed. The bits in the ...
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Error bit (DQ5) The error bit can be used to identify errors detected by the program/erase controller. The error bit is set to ’1’ when a program, block erase or chip erase operation fails to write the correct data ...
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Table 8. Status register bits Operation Address Program Any address Program during Any address erase suspend Program error Any address Chip erase Any address Erasing block Block erase before timeout Non-erasing block Erasing block Block erase Non-erasing block Erasing block ...
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Figure 11. Toggle flowchart 30/56 START READ DQ6 READ DQ5 & DQ6 DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 TWICE DQ6 NO = TOGGLE YES FAIL PASS AI01370C ...
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Maximum rating Stressing the device above the rating listed in the cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the ...
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DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement ...
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Figure 13. AC measurement load circuit V CC 0.1µ includes JIG capacitance Table 11. Device capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Table 12. DC characteristics Symbol Parameter ...
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Figure 14. Read mode AC waveforms A0-A18/ A– DQ0-DQ7/ DQ8-DQ15 BYTE tELBL/tELBH Table 13. Read AC characteristics Symbol Alt Parameter t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ...
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Figure 15. Write AC waveforms, write enable controlled A0-A18/ A–1 E tELWL G tGHWL W DQ0-DQ7/ DQ8-DQ15 V CC tVCHEL RB Table 14. Write AC characteristics, write enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV ...
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Figure 16. Write AC waveforms, chip enable controlled A0-A18/ A–1 W tWLEL G tGHEL E DQ0-DQ7/ DQ8-DQ15 V CC tVCHWL RB Table 15. Write AC characteristics, chip enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV ...
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Figure 17. Reset/block temporary unprotect AC waveforms tPLPX RP Table 16. Reset/block temporary unprotect AC characteristics Symbol Alt (2) t PHWL RP High to Write Enable Low, Chip Enable t t PHEL RH Low, Output Enable ...
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Package mechanical data In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. ECOPACK® packages are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance ...
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Figure 19. TFBGA48 6x8mm – ball array - 0.80 mm pitch, bottom view package outline FD FE BALL "A1" Drawing is not to scale. Table 18. TFBGA48 6 x 8mm – 6 ...
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... Ordering information Table 19. Ordering information scheme Example: Device type M29 Parallel Flash Memory Operating voltage 3.6 V main family Device function 800F = 8 Mbit memory array, (× 8, × 16) 400F = 4 Mbit memory array (× 8, × 16) Array matrix T = Top boot B = Bottom boot Speed Class ...
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For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 41/56 ...
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Appendix A Block address table Table 20. Top boot block addresses, M29W800FT # Size (Kbytes ...
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Table 21. Bottom boot block addresses, M29W800FB # Size (Kbytes) Address range (× ...
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Table 22. Top boot block addresses M29W400FT # Size (Kbytes Table 23. Bottom boot block addresses M29W400FB # ...
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... Common Flash interface (CFI) The common Flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary ...
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Table 25. CFI query identification string Address 10h 20h 0051h 11h 22h 0052h 12h 24h 0059h 13h 26h 0002h 14h 28h 0000h 15h 2Ah 0040h 16h 2Ch 0000h 17h 2Eh 0000h 18h 30h 0000h 19h 32h ...
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... Table 27. Device geometry definition Address Data × 16 × 8 27h 4Eh 0014h Device size = 2 28h 50h 0002h Flash device interface code description 29h 52h 0000h 2Ah 54h 0000h Maximum number of bytes in multi-byte program or page = n 2 2Bh 56h 0000h Number of erase block regions within the device. ...
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Table 28. Primary algorithm-specific extended query table Address × 16 × 8 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah 94h 4Bh 96h 4Ch 98h Table 29. ...
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... Block protection Block protection can be used to prevent any operation from modifying the data stored in the Flash. Each block can be protected individually. Once protected, program and erase operations on the block fail to change the data. There are three techniques that can be used to control block protection, these are the programmer technique, the in-system technique and temporary unprotection. Temporary unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP ...
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Table 30. Programmer technique bus operations, BYTE = V Operation E G Block protect Chip unprotect Block protection verify Block unprotection verify 50/56 Address ...
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Figure 20. Programmer equipment block protect flowchart ADDRESS = BLOCK ADDRESS START Wait 4µ Wait 100µ ...
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Figure 21. Programmer equipment chip unprotect flowchart NO 52/56 START PROTECT ALL BLOCKS CURRENT BLOCK = 0 A6, A12, A15 = Wait 4µ Wait ...
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Figure 22. In-system equipment block protect flowchart ADDRESS = BLOCK ADDRESS ADDRESS = BLOCK ADDRESS ...
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Figure 23. In-system equipment chip unprotect flowchart ISSUE READ/RESET 54/56 START PROTECT ALL BLOCKS CURRENT BLOCK = WRITE 60h ANY ADDRESS WITH ...
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Revision history Table 31. Document revision history Date Revision 19-Feb-2007 17-Mar-2008 28-Mar-2008 26-May-2009 22-Feb-2010 19-July-2010 1 Initial release. 2 Added TFBGA package. Minor text changes. 3 Applied Numonyx branding. 4 Added support for 400FT/B Changes cover page as following: ...
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... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...