MD2211-D16-V3 SanDisk, MD2211-D16-V3 Datasheet - Page 14

• Manufacturer Part Number: MD2211-D16-V3
• Manufacturer: SanDisk
• Type: Flash Diskr

Specifications of MD2211-D16-V3

• Density: 16MByte
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Package Type: TSOP-I
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Supplier Unconfirmed

6
6.1
DiskOnChip 2000 TSOP devices are reset by the RSTIN# input. When the reset signal is negated, the
DiskOnChip initiates the download procedure from the flash memory into the internal XIP boot block.
Hosts may employ any of the following methods to guarantee the timing requirements of the first access to the
DiskOnChip 2000 TSOP:
a) Use a software loop to wait at least T
b) Poll the state of the BUSY# output.
c) Use the BUSY# output to hold the host before first access.
Host systems that boot from the DiskOnChip 2000 TSOP must employ option c), or use another method to
guarantee the required timing of the first access. (Refer to Figure 5 and Table 8).
Note: CPU_CYCLE# is an imaginary signal that is low during a CPU write or read cycle. It is equivalent to: !(!CE# & (!WE# | !OE#)).
Table 8: Timing Specifications
Note 1: Max value is specified from the first positive crossing above 2.15V to the final positive crossing above 3.0V. Min value is
specified from 0V to 2.7V. Slew rate not to exceed 0.33 V/uS at any time.
Note 2: Specified from the final positive crossing of Vcc above 3.0V.
Note 3: If the assertion of RSTIN# occurs during a flash erase cycle this time could be extended by up to 500 s.
Note 4: Normal read/write cycle timing applies. This parameter applies only to the case when the cycle is extended until the negation
of the BUSY# signal.
91-SR-002-32-8L Rev. 0.2
Parameter
VCC_RISE
Trec(VCC-RSTIN)
Tw(RSTIN#)
Tp(BUSY0)
Tp(BUSY1)
Tho(BUSY-CS)
Tsu(D-BUSY1)
negated.
Timing Specifications
Power-up Timing
D (Read cycle)
CPU_CYCLE#
RSTIN#
BUSY#
VCC = 3.0V
VCC rise time
VCC stable to RSTIN# á
RSTIN# asserted pulse width
RSTIN# â
RSTIN# á
BUSY# á to CE#/OE#/WE# á
Data valid to BUSY# á
VCC
T
to BUSY# á
to BUSY# â
REC
P
(VCC-RSTIN)
Figure 5: Reset Timing
Description
(BUSY1) before accessing the DiskOnChip after the reset signal is
PRELIMINARY
T
SU
(D-BUSY1)
T
P
(BUSY1)
T
HO
(BUSY-CS)
DiskOnChip 2000 TSOP 16MB Data Sheet
0.01
Min
100
T
30
0
0
P
(BUSY0)
T
W
(RSTIN)
Max
32.7
50
1
Units
ms
ms
ns
ns
ns
ns
ns
Notes
1
2
3
4
4
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