SLATA5GM1U STEC, SLATA5GM1U Datasheet - Page 7

• Manufacturer Part Number: SLATA5GM1U
• Manufacturer: STEC

Specifications of SLATA5GM1U

• Lead Free Status / RoHS Status: Compliant

SLATAxxx(M/G)M1U(I)
Datasheet
-CSEL
(PC Card Memory Mode)
-CSEL
(PC Card I/O Mode)
-CSEL
(True IDE Mode)
-REG
(PC Card Memory Mode)
Attribute Memory Select
-REG
(PC Card I/O Mode)
-DMACK (not used for part
numbers with P)
(True IDE Mode)
WP
(PC Card Memory Mode)
Write Protect
-IOIS16
(PC Card I/O Mode)
-IOIS16
(True IDE Mode)
-INPACK
(PC Card Memory Mode)
-INPACK
(PC Card I/O Mode)
Input Acknowledge
DMARQ (Not used for part
numbers with P)
(True IDE Mode)
BVD1
(PC Card Memory Mode)
-STSCHG
(PC Card I/O Mode)
Status Changed
-PDIAG
(True IDE Mode)
Signal Name
I
I
O
O
I/O
Type
56
61
33
60
63
Number
61000-04497-104, January 2007
Pin
This signal is not used for this mode.
This signal is not used for this mode.
This signal is used to configure this ATA PC Card as a
Master or Slave. By default (ball not connected), the ATA PC
Card is configured as a Master. To configure the ATA PC
Card as a Slave, pull up ball to VCC through 0 to 470 ohm
resistor.
This signal distinguishes between accesses to Common
Memory (high) and Register Attribute Memory (low).
The signal must also be active (low) during I/O Cycles when
the I/O address is on the bus.
In True IDE Mode this input signal is used by host in
response to DMARQ to initiate DMA transfers.
The ATA PC Card does not have a write protect switch;
therefore, this signal is held low after the completion of the
reset initialization sequence.
A low signal indicates that a 16 bit or odd byte only operation
can be performed at the addressed port.
Not defined in IDE Mode.
This signal is not used in this mode.
The Input Acknowledge signal is asserted by the ATA PC
Card when it is selected and responding to an I/O read cycle
at the address that is on the bus. The host uses this signal to
control the enable of any input data buffers between the ATA
PC Card and the host’s CPU.
In True IDE Mode this signal is asserted by the ATA PC
Card when it is ready to transfer data to/from the host. Data
direction is controlled by -IORD and -IOWR. This signal is
used in a handshake manner with -DMACK.
This signal is asserted high as since a battery is not used
with this product.
This signal is asserted low to alert the host to changes in the
RDY/-BSY and Write Protect states. Its use is controlled by
the Configuration and Status Register.
In True IDE Mode, this input/output signal is the Pass
Diagnostic signal in the Master/Slave handshake protocol.
Description
ATA PC Card
7