MT45W2MW16PGA-70 IT Micron Technology Inc, MT45W2MW16PGA-70 IT Datasheet - Page 9

• Manufacturer Part Number: MT45W2MW16PGA-70 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16PGA-70 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Functional Description
Power-Up Initialization
Figure 4:
Bus Operating Modes
Asynchronous Mode
PDF: 09005aef82832fa7 / Source: 09005aef82832f97
32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 12/09 EN
Power-Up Initialization Timing
In general, the MT45W2MW16P device is a high-density alternative to SRAM and Pseudo
SRAM products, popular in low-power, portable applications. The MT45W2MW16P
contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by 16 bits. These
devices include the industry-standard, asynchronous memory interface found on other
low-power SRAM or Pseudo SRAM offerings. Page mode accesses are also included as a
bandwidth-enhancing extension to the asynchronous read protocol.
CellularRAM products include an on-chip voltage sensor that is used to launch the
power-up initialization process. Initialization will load the CR with its default setting.
V
1.7V, the device will require 150µs to complete its self-initialization process (see
Figure 4). During the initialization period, CE# should remain HIGH. When initialization
is complete, the device is ready for normal operation.
The MT45W2MW16P CellularRAM product incorporates the industry-standard, asyn-
chronous interface found on other low-power SRAM or Pseudo SRAM offerings. This bus
interface supports asynchronous READ and WRITE operations as well as the band-
width-enhancing page mode READ operation. The specific interface that is supported is
defined by the value loaded into the CR.
CellularRAM products power up in the asynchronous operating mode. This mode uses
the industry-standard SRAM control interface (CE#, OE#, WE#, LB#/UB#). READ opera-
tions (Figure 5) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping
WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has
elapsed. WRITE operations (Figure 6) occur when CE#, WE#, and LB#/UB# are driven
LOW. During WRITE operations, the level of OE# is a “Don't Care”; WE# will override
OE#. The data to be written will be latched on the rising edge of CE#, WE#, or LB#/UB#,
whichever occurs first. WE# LOW time must be limited to
Vcc, VccQ = 1.7V
CC
and V
CC
Q must be applied simultaneously, and when they reach a stable level above
32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory
t PU
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
normal operation
Device ready for
Vcc (MIN)
t
CEM.
Functional Description
©2007 Micron Technology, Inc. All rights reserved.