MT45W2MW16BGB-701 WT Micron Technology Inc, MT45W2MW16BGB-701 WT Datasheet - Page 52

• Manufacturer Part Number: MT45W2MW16BGB-701 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16BGB-701 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Figure 41:
PDF: 09005aef82832fa2/Source: 09005aef82832f5f
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN
DQ[15:0]
LB#/UB#
A[20:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IH
IL
IH
IL
IH
IL
OH
OL
IL
IH
IL
Output Delay in Continuous Burst WRITE with BCR[8] = 0 for End-of-Row Condition
Notes:
t CLK
Valid input
t SP
1. Nondefault BCR settings for continuous burst WRITE, BCR[8] = 0; WAIT active LOW; WAIT
2. CE# must not remain LOW longer than
3. WAIT asserts anywhere from LC to 2LC cycles. LC = latency code (BCR[13:11]).
4. Taking CE# HIGH or ADV# LOW on the start-of-row cycle will abort the burst and not write
(A[6:0] = 7Fh)
End of row
asserted during delay. Do not cross row boundaries with fixed latency.
the start-of-row data. Devices from different CellularRAM vendors can assert WAIT so that
the start-of-row data is input just before (as shown) or just after WAIT asserts. This differ-
ence in behavior will not be noticed by controllers that monitor WAIT or that use WAIT to
abort on the start-of-row input cycle.
t HD
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Valid input
Start of row
(A[6:0] = 00h)
(Note 4)
t KHTL
Note 4
Note 3
52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CEM.
t KHTL
©2007 Micron Technology, Inc. All rights reserved.
Valid input
Timing Diagrams
Don’t Care
Valid input