MT45W2MW16PFA-70 Micron Technology Inc, MT45W2MW16PFA-70 Datasheet - Page 6

• Manufacturer Part Number: MT45W2MW16PFA-70
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16PFA-70

• Lead Free Status / RoHS Status: Not Compliant

Table 1:
Table 2:
PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f
AsyncCellularRAM_2.fm - Rev. G 10/05 EN
Mode
Standby
Read
Write
No Operation
PAR
DPD
Load
Configuration
Register
G4, G3, H5, H4,
E3, H6, G2, H1,
H3, H2, D4, C4,
C3, B4, B3, A5,
D2, C2, C1, B1,
D3, E4, F4, F3,
G1, F1, F2, E2,
G6, F6, F5, E5,
D5, C6, C5, B6
Assignment
VFBGA Ball
A4, A3
A6
B5
A2
G5
A1
B2
D6
D1
E1
E6
VFBGA Ball Descriptions
Bus Operations
Partial-Array Refresh
DQ[15:0]
Symbol
A[21:0]
Deep Power-Down
V
V
WE#
OE#
UB#
ZZ#
CE#
LB#
V
V
CC
SS
Notes: 1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# only is in
CC
SS
Q
Q
Standby
Power
Active
Active
Active
Idle
2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data
3. When WE# is invoked, the OE# input is internally disabled and has no effect on the I/Os.
4. The device will consume active power in this mode whenever addresses are changed.
5. V
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
Output
Supply
Supply
Supply
Supply
Input/
Input
Input
Input
Input
Input
Input
Input
Type
select mode, only DQ[7:0] are affected. When UB# only is in the select mode, DQ[15:8] are
affected.
inputs/outputs are internally isolated from any external influence.
standby current.
IN
= V
CC
Address Inputs: Inputs for the address accessed during READ or WRITE operations.
The address lines are also used to define the value to be loaded into the CR.
Sleep Enable: When ZZ# is LOW, the CR can be loaded or the device can enter one
of two low-power modes (DPD or PAR).
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby power mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Write Enable: Enables WRITE operations when LOW.
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Data Inputs/Outputs.
Device Power Supply: (1.70V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.70V–3.30V) Power supply for input/output buffers.
V
V
Q or 0V; all device balls must be static (unswitched) in order to achieve minimum
SS
SS
CE#
Q must be connected to ground.
H
H
H
L
L
L
L
must be connected to ground.
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0 Memory
WE#
H
X
X
X
X
L
L
6
OE#
X
X
X
X
X
X
L
LB#/UB#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
X
X
X
X
L
L
Description
ZZ#
H
H
H
H
L
L
L
General Description
©2003 Micron Technology, Inc. All rights reserved.
DQ[15:0]
Data-Out
Data-In
High-Z
High-Z
High-Z
High-Z
X
1
Notes
1, 3, 4
2, 5
1, 4
4, 5
6
6