SL72A8M64M8M-C75EWU STEC, SL72A8M64M8M-C75EWU Datasheet

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SL72A8M64M8M-C75EWU

Manufacturer Part Number
SL72A8M64M8M-C75EWU
Description
Manufacturer
STEC
Datasheet

Specifications of SL72A8M64M8M-C75EWU

Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
512Mb
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.395A
Number Of Elements
9
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Compliant
64M X 72 Bits (512MB) 200-Pin DDR SDRAM SO-DIMM with ECC (PC2100)
FEATURES
PACKAGE DIMENSIONS
Units are in inches (millimeters). Tolerances are ±0.005 (±0.127) unless otherwise specified.
www.stec-inc.com
• PC2100 Compliant
• 200-Pin SO-DIMM form factor
• Auto and self refresh capability
• SSTL_2 compatible inputs and outputs
• +2.5V + 0.2V V
• DDR architecture: Two data accesses per clock cycle,
• Four internal banks for concurrent operation
• Auto Precharge option for each burst access
• Burst lengths: 2, 4, 8
• All inputs are sampled at the positive going edge of the
• Serial Presence Detect with EEPROM
• ECC
• RoHS Compliant, lead-free version available
(DDR266A 133MHz-7.5ns@CL = 2)
(DDR266B 133MHz-7.5ns@CL = 2.5)
(8192 cycles/64ms refresh)
differential clock inputs (CK0 and /CK0), and bi-
directional data strobe (DQS)
system clock; data referenced to both edges of DQS
0.078 (1.98) R Min
2 Places
DD
1
(See Detail A)
2
Voltage Key
SDRAM
SDRAM
SDRAM
SDRAM
39
40
DDR
DDR
DDR
DDR
41
42
(67.60)
2.661
EEPROM
0.024
(0.60)
SDRAM
SDRAM
SDRAM
SDRAM
DDR
DDR
DDR
DDR
(Where x = CAS Latency; U selects RoHS Compliant, lead-free version.)
Document Part Number 61000-02305-107 July 2007 Page 1
200
GENERAL DESCRIPTION
The SL72A8M64M8M-C75xW(U) is a 64M x 72 bit Double Data
Rate (DDR) Synchronous Dynamic RAM (SDRAM) Small-
Outline Dual In-line Memory Module (SO-DIMM).
The module consists of nine CMOS 16M x 8 bit x 4 bank DDR
SDRAMs in 66-pin 400-mil TSOP II packages mounted on a
200-pin glass epoxy substrate.
A serial EEPROM using the two pin I
mounted to provide for the Serial Presence Detects (SPD).
Decoupling capacitors of 0.22μF are mounted. Damping
resistors are mounted for DQ, DQS, and DM signals. A PLL
supplies clocks to the SDRAMs from one clock input.
The module has gold edge connections and is intended for
mounting into 200-pin SO-DIMM edge connector sockets keyed
for 2.5V.
ORDERING INFORMATION
199
Part Number
SL72A8M64M8M-C75DW(U)
SL72A8M64M8M-C75EW(U)
Note: The “U” suffix added to the part number selects the
RoHS Compliant, lead-free module.
SL72A8M64M8M-C75xW(U)
(20.00)
0.790
0.039±0.003
(1.00±0.08)
(31.75)
1.250
0.039±0.004
Left Key Position:
(1.00±0.10)
V
DD
=V
Detail A
DD
0.071
(1.80)
Q=2.5V
2.5
CL
0.059 (1.50) MAX
Full Radius
2
0.059 (1.50) MAX
0.157±0.004
(4.00±0.10)
2
MHz
133
133
C protocol is also
Bandwidth
2.1 GB/s
2.1 GB/s
1195

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SL72A8M64M8M-C75EWU Summary of contents

Page 1

... SL72A8M64M8M-C75xW(U) (Where x = CAS Latency; U selects RoHS Compliant, lead-free version.) GENERAL DESCRIPTION The SL72A8M64M8M-C75xW( 64M x 72 bit Double Data Rate (DDR) Synchronous Dynamic RAM (SDRAM) Small- Outline Dual In-line Memory Module (SO-DIMM). The module consists of nine CMOS 16M x 8 bit x 4 bank DDR SDRAMs in 66-pin 400-mil TSOP II packages mounted on a 200-pin glass epoxy substrate ...

Page 2

... SL72A8M64M8M-C75xW(U) (Where x = CAS Latency; U selects RoHS Compliant, lead-free version.) PIN CONFIGURATION (* = Not Used Active Low) Pinout Pin Front Pin Back Pin REF REF DQS \DQS DQS \DQS / DQS \DQS Pin Description Pin Symbol Pin Function CK Clock inputs, positive line (0:2) /CK Clock inputs, negative line ...

Page 3

... SL72A8M64M8M-C75xW(U) (Where x = CAS Latency; U selects RoHS Compliant, lead-free version.) FUNCTIONAL BLOCK DIAGRAM / 0-7 / DQS DQS \DQS 8-15 / DQS DQS \DQS 16- DQS DQS \DQS 24- DQS DQS \DQS 0 DQS DQS \DQS /AP /AP SDRAMs U0- SDRAMs U0- /RAS: SDRAMs U0-U8 /RAS /CAS: SDRAMs U0-U8 ...

Page 4

... SL72A8M64M8M-C75xW(U) (Where x = CAS Latency; U selects RoHS Compliant, lead-free version.) SERIAL PRESENCE DETECT INFORMATION 2 Serial PD Interface Protocol Current sink capability of SDA driver <=3mA; Maximum clock frequency: 100 KHz Byte # Function Described bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device ...

Page 5

... SL72A8M64M8M-C75xW(U) (Where x = CAS Latency; U selects RoHS Compliant, lead-free version.) SERIAL PRESENCE DETECT INFORMATION Byte # Function Described 36-40 Superset information (may be used in future) 41 Row cycle time ( Auto refresh cycle time (t RFC 43 Maximum SDRAM device cycle time (t 44 DQS-DQ skew (t ) DQSQ 45 SDRAM device data hold skew factor (t ...

Page 6

... SL72A8M64M8M-C75xW(U) (Where x = CAS Latency; U selects RoHS Compliant, lead-free version.) ABSOLUTE MAXIMUM RATINGS Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional Operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time may affect device reliability. ...

Page 7

... SL72A8M64M8M-C75xW(U) (Where x = CAS Latency; U selects RoHS Compliant, lead-free version.) DC CHARACTERISTICS (Recommended operating conditions unless otherwise noted; Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.) Parameter/Condition OPERATING CURRENT: One bank; Active-Precharge (MIN (MIN); DQ, DM and DQS inputs changing once per clock cyle ...

Page 8

... SL72A8M64M8M-C75xW(U) (Where x = CAS Latency; U selects RoHS Compliant, lead-free version.) AC OPERATING TEST CONDITIONS (V =V Q=2.5V, T =0°C to 70° Parameter Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate Input levels ( Input timing measurement ref. level Output timing measurement ref ...

Page 9

... SL72A8M64M8M-C75xW(U) (Where x = CAS Latency; U selects RoHS Compliant, lead-free version.) AC TIMING PARAMETERS Symbol Parameter tRC Row cycle time t RFC Refresh row cycle time tRAS Row active time tRCD /RAS to /CAS delay tRP Row precharge time tRRD Row active to Row acitve delay tWR ...

Page 10

... SL72A8M64M8M-C75xW(U) (Where x = CAS Latency; U selects RoHS Compliant, lead-free version.) Notes: 1. Maximum burst refresh The specific requirement is that DQS be valid(High or Low before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus previous write was in progress, DQS could be High at this time, depending on tDQSS ...

Page 11

... SL72A8M64M8M-C75xW(U) (Where x = CAS Latency; U selects RoHS Compliant, lead-free version.) REVISION HISTORY Rev. Change Description from Previous Revision -103 03/24/2004. Component-based specs added. -104 03/25/2004. Board updated from PCB 955 (1.400") to PCB 1195 (1.250"). -105 04/12/2004. CK1 and CK2 termination removed from block ...

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