M395T5750EZ4CE65 Samsung Semiconductor, M395T5750EZ4CE65 Datasheet - Page 6

• Manufacturer Part Number: M395T5750EZ4CE65
• Manufacturer: Samsung Semiconductor

Specifications of M395T5750EZ4CE65

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240FBDIMM
• Device Core Size: 72b
• Organization: 256Mx72
• Total Density: 2GByte
• Chip Density: 512Mb
• Package Type: FBDIMM
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Number Of Elements: 36
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

2.2 FB-DIMM Channel Frequency Scaling
There are many frequency parameters including reference clock frequency, DRAM clock frequency, DRAM data transfer rate, channel
transfer rate and channel unit interval. All of frequency parameters are scaled with a certain gear ratio. External clock source provides
reference clock input to AMB and Host. External clock source is relatively slower than channel and DRAM frequency. Thus, AMB dou-
bles external clock input and generates clock inputs to DRAMs. DRAM use clock input from AMB which is two times faster than refer-
ence clock for DRAM operation. DRAM data transfer rate is two times faster than DRAM clock input with nature of double data rate
operation and four times faster than external clock source. Channel speed is represented by unit interval - average time interval between
voltage transitions of a signal in the FBD channel. It is six times faster than DRAM data transfer rate. For example, external clock source
gives 6ns clock (166MHz), AMB doubles it and gives 3ns clock (333MHz) to DRAM and FBD channel communicate with unit interval -
250ps (4.0Gbps transfer rate).
FBDIMM
Figure 2 : FB-DIMM Speed Scaling
Figure 2 shows frequency scale ratio over frequency parameters in FBD memory system.
DDR2-533
DDR2-667
DDR2-800
DDR667 Ex.
6ns
3ns
250ps
Reference CLK
CLK_REF
CLK_DRAM
Packet T/F
Host
208.33ps
312.5ps
250ps
UI
12 UIs in one CLK_DRAM
Clock
SB (ADDR, CMD, Wdata)
CLK_DRAM
NB(Rdata)
266MHz
333MHz
400MHz
6 of 33
Reference CLK
CLK_REF
133MHz
166MHz
200MHz
Rx
Tx
Clk_Ref
DQs ADDR
DRAM
DRAM
DRAM
DRAM
AMB
CMD
Frequency
3.2Gb/s
4.0Gb/s
4.8Gb/s
CLK
Rev. 1.51 January 2008
Rx
Tx
DDR2 SDRAM