MT16VDDT6464AG-265CA Micron Technology Inc, MT16VDDT6464AG-265CA Datasheet - Page 10

• Manufacturer Part Number: MT16VDDT6464AG-265CA
• Manufacturer: Micron Technology Inc

Specifications of MT16VDDT6464AG-265CA

• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.232A
• Number Of Elements: 16
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Not Compliant

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Table 10:
PDF: 09005aef80739fa5/Source:09005aef807397e5
DD16C64_128_256x64A.fm - Rev. E 8/08 EN
Parameter/Condition
Operating one bank active-precharge current:
(MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
cycle
Precharge power-down standby current: All device banks idle; Power-down
mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
Active power-down standby current: One device bank active; Power-down
mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device bank
active; Address and control inputs changing once per clock cycle;
I
Operating burst write current: BL = 2; Continuous burst writes; One device
bank active; Address and control inputs changing once per clock cycle;
t
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving reads
(BL = 4) with auto precharge;
control inputs change only during active READ or WRITE commands
DD
CK =
RAS (MAX);
OUT
CK =
IN
= V
= 0mA
Specifications
t
t
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
REF
t
t
CK =
CK =
for DQ, DM, and DQS
t
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
CK =
I
Values are for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
DD
OUT
Specifications and Conditions – 512MB (Die Revision K)
t
Notes:
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
= 0mA; Address and control inputs changing once per clock
1. Value calculated as one module rank in this operating condition; all other module ranks in
2. Value calculated reflects all module ranks in this operating condition.
t
RC =
I
DD
2P (CKE LOW) mode.
t
RC (MIN);
512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
t
CK =
t
RC =
t
CK (MIN); Address and
t
RC (MIN);
t
t
t
CK =
REFC =
REFC = 7.8125µs
10
t
t
CK (MIN);
RC =
t
CK =
t
RFC (MIN)
t
CK =
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RC (MIN);
t
CK (MIN);
t
CK
t
RC =
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1
1
2
2
1
Electrical Specifications
2
2
2
1
2
2
1
1,472
1,472
2,560
2,352
©2004 Micron Technology, Inc. All rights reserved
-40B
832
992
800
560
960
64
96
64
1,132
1,312
2,560
2,192
-335
752
952
800
480
880
64
96
64
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA