MT36HVZS51272PY-667E1 Micron Technology Inc, MT36HVZS51272PY-667E1 Datasheet - Page 12

• Manufacturer Part Number: MT36HVZS51272PY-667E1
• Manufacturer: Micron Technology Inc

Specifications of MT36HVZS51272PY-667E1

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 512Mx72
• Total Density: 4GByte
• Chip Density: 1Gb
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 2.376A
• Number Of Elements: 36
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

Table 11: DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (512 Meg
x 4) component data sheet
PDF: 09005aef83e49b25
hv-z-s36c256_512x72py.pdf - Rev. D 03/10 EN
Parameter
Operating one bank active-precharge current:
(I
mands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
4, CL = CL (I
(I
Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
=
puts are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
mands; Other control and address bus inputs are switching; Data bus in-
puts are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, I
MAX (I
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
(I
trol and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
RAS MAX (I
RP =
DD
DD
DD
t
CK (I
),
),
) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
t
t
t
RAS =
RCD =
RP (I
OUT
DD
DD
),
); CKE is LOW; Other control and address bus in-
= 0mA; BL = 4, CL = CL (I
DD
t
DD
RP =
DD
t
t
); CKE is HIGH, S# is HIGH between valid commands; Address
RAS MIN (I
RCD (I
), AL = 0;
),
t
t
RP =
RP (I
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands;
t
RP (I
Specifications and Conditions – 4GB
t
DD
DD
CK =
t
); CKE is HIGH, S# is HIGH between valid com-
CK =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid com-
DD
t
); CKE is HIGH, S# is HIGH between valid com-
CK (I
t
CK (I
DD
DD
DD
t
CK =
),
), AL = 0;
2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM
); REFRESH command at every
t
RC =
t
CK (I
t
RC (I
t
DD
CK =
),
DD
t
CK =
t
t
RAS =
CK =
),
t
t
CK (I
CK =
t
RAS =
t
CK
t
CK (I
t
DD
CK (I
t
OUT
t
CK =
t
DD4W
RAS MAX (I
t
CK (I
CK =
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
),
12
t
DD
RAS MIN
t
= 0mA; BL =
DD
RAS =
),
t
DD
CK (I
),
t
t
CK (I
); CKE is
RAS =
t
RC =
t
RFC
t
DD
RAS
DD
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
);
t
),
);
RC
Combined
Symbol
I
I
I
I
I
I
CDD4W
I
I
CDD2Q
CDD2N
CDD3N
I
I
I
CDD2P
CDD3P
CDD0
CDD1
DD4R
CDD5
CDD6
1
1
1
2
2
2
2
2
2
2
1
-80E/
-800
1836
2196
1026
1116
1296
2826
2826
4446
252
846
306
252
© 2006 Micron Technology, Inc. All rights reserved.
I
DD
-667
1746
2016
1206
2376
2376
4086
252
846
936
666
306
252
Specifications
-53E
1476
1926
1026
2196
2196
3996
252
846
936
666
306
252
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA