MT8LSDT3264AG-133D2 Micron Technology Inc, MT8LSDT3264AG-133D2 Datasheet - Page 9

• Manufacturer Part Number: MT8LSDT3264AG-133D2
• Manufacturer: Micron Technology Inc

Specifications of MT8LSDT3264AG-133D2

• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.08A
• Number Of Elements: 8
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Not Compliant

Mode Register Definition
Burst Length
Burst Type
PDF: 09005aef807b3771/Source: 09005aef807b37b5
SD8_16C32_64x64AG.fm - Rev. D 3/05 EN
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least
through the end of this period, Command Inhibit or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least one Command Inhibit or NOP com-
mand having been applied, a PRECHARGE command should be applied. All device
banks must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO refresh cycles must be performed. After the AUTO
refresh cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of a burst length, a burst type, a CAS latency, an operat-
ing mode and a write burst mode, as shown in the Mode Register Definition Diagram.
The mode register is programmed via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the oper-
ating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future
use.
The mode register must be loaded when all device banks are idle, and the controller
must wait the specified time before initiating the subsequent operation. Violating either
of these requirements will result in unspecified operation.
Read and write accesses to the SDRAM are burst oriented, with the burst length being
programmable, as shown in Mode Register Definition Diagram. The burst length deter-
mines the maximum number of column locations that can be accessed for a given READ
or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page burst is available for the
sequential type. The full-page burst is used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached, as shown in
the Burst Definition Table. The block is uniquely selected by A1–A9 when the burst
length is set to two; by A2–A9 when the burst length is set to four; and by A3–A9 when the
burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to
select the starting location within the block. Full-page bursts wrap within the page if the
boundary is reached, as shown in Table 7, Burst Definitions, on page 11.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 7, Burst Definitions, on page 11.
256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Mode Register Definition
©2003 Micron Technology, Inc. All rights reserved.