CY14B104N-ZSP45XCES Cypress Semiconductor Corp, CY14B104N-ZSP45XCES Datasheet - Page 5

• Manufacturer Part Number: CY14B104N-ZSP45XCES
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of CY14B104N-ZSP45XCES

• Word Size: 16b
• Density: 4Mb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Mounting: Surface Mount
• Supply Current: 50mA
• Lead Free Status / RoHS Status: Compliant

Hardware RECALL (Power Up)
During
(V
V
cycle is automatically initiated and takes t
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14B104L/CY14B104N
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
Table 1. Mode Selection
Notes
Document #: 001-07102 Rev. *I
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
4. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
5. While there are 19 address lines on the CY14B104L/CY14B104N, only the lower 16 lines are used to control software modes.
6. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
CC
CC
< V
again exceeds the sense voltage of V
CE
SWITCH
H
L
L
L
L
power
), an internal RECALL request is latched. When
up
or
after
WE
X
H
H
H
L
any
low
HRECALL
SWITCH
power
OE
X
X
L
L
L
PRELIMINARY
to complete.
, a RECALL
condition
A15 - A0
0xB1C7
0x7C1F
0xB1C7
0x7C1F
0x4E38
0x83E0
0x703F
0x8B45
0x4E38
0x83E0
0x703F
0x4B46
X
X
X
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important to use read cycles and not write cycles
in the sequence, although it is not necessary that OE be LOW
for a valid sequence. After the t
SRAM is activated again for the read and write operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the t
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
AutoStore Enable
Not Selected
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Write SRAM
AutoStore
Disable
Mode
CY14B104L, CY14B104N
RECALL
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Input Data
STORE
cycle time, the SRAM is again
IO
cycle time is fulfilled, the
Active
Active
Standby
Page 5 of 23
Power
Active
Active
[4,5,6]
[4,5,6]
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