STK14C88-3N45 Cypress Semiconductor Corp, STK14C88-3N45 Datasheet - Page 11

• Manufacturer Part Number: STK14C88-3N45
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK14C88-3N45

• Word Size: 8b
• Organization: 32Kx8
• Density: 256Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOIC
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Surface Mount
• Supply Current: 42mA
• Lead Free Status / RoHS Status: Not Compliant

Switching Waveforms
Document Number: 001-50592 Rev. *B
Table 3. SRAM Write Cycle
t
t
t
t
t
t
t
t
t
t
Notes
WC
PWE
SCE
SD
HD
AW
SA
HA
HZWE
LZWE
12. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
13. CE or WE must be greater than V
14. HSB must be HIGH during SRAM WRITE cycles.
Parameter
Cypress
[11]
[11,12]
ADDRESS
DATA OUT
ADDRESS
DATA OUT
DATA IN
DATA IN
WE
CE
CE
WE
Parameter
t
t
t
t
t
t
t
t
t
t
AVAV
WLWH,
ELWH,
DVWH,
WHDX,
AVWH,
AVWL,
WHAX,
WLQZ
WHQX
t
t
t
t
t
t
t
ELEH
AVEL
AVEH
EHAX
WLEH
DVEH
EHDX
Alt
IH
during address transitions.
PREVIOUS DATA
t
SA
Figure 10. SRAM Write Cycle 2: CE Controlled
Figure 9. SRAM Write Cycle 1: WE Controlled
t
SA
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
Description
HIGH IMPEDANCE
t
t
AW
t
PWE
AW
t
HZWE
t
t
t
SCE
SCE
WC
t
WC
t
t
HIGH IMPEDANCE
PWE
SD
DATA VALID
DATA VALID
t
SD
Min
[13, 14]
[13, 14]
35
25
25
12
25
0
0
0
5
t
HA
t
t
t
35 ns
HD
HA
HD
Max
13
t
LZWE
Min
45
30
30
15
30
0
0
0
5
STK14C88-3
45 ns
Max
15
Page 11 of 17
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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