STK14CA8-N35I Cypress Semiconductor Corp, STK14CA8-N35I Datasheet - Page 3

• Manufacturer Part Number: STK14CA8-N35I
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK14CA8-N35I

• Word Size: 8b
• Organization: 128Kx8
• Density: 1Mb
• Interface Type: Parallel
• Access Time (max): 35ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOIC
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: -40C to 85C
• Pin Count: 32
• Mounting: Surface Mount
• Supply Current: 60mA
• Lead Free Status / RoHS Status: Not Compliant

Pinouts
Pin Descriptions
Document Number: 001-51592 Rev. *C
Note
2. See
Pin Name
DQ
A
V
HSB
V
16
V
NC
7
W
CAP
G
E
CC
-DQ
SS
-A
Package Diagrams
0
0
Power Supply
Power Supply
Power Supply
V
DQ
DQ
DQ
No Connect
NC
NC
NC
NC
V
NC
CAP
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
Figure 1. 48-Pin SSOP
SS
16
14
12
7
6
3
2
1
0
5
4
0
1
2
Input
Input
Input
Input
I/O
I/O
I/O
on page 16 for detailed package size specifications.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array.
Data: Bi-directional 8-bit data bus for accessing the nvSRAM.
Chip Enable: The active low E input selects the device.
Write Enable: The active low W allows to write the data on the DQ pins to the address location
latched by the falling edge of E.
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high causes the DQ pins to tri-state.
Power: 3.0V, +20%, -10%.
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection is optional).
AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
Ground.
Unlabeled pins have no internal connections.
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
NC
NC
NC
NC
NC
NC
DQ
G
E
DQ
DQ
DQ
DQ
V
HSB
W
A
A
A
A
V
A
V
A
13
9
11
SS
10
CC
CC
15
8
6
7
5
4
3
Description
Figure 3. Relative PCB Area Usage
V
DQ
DQ
DQ
V
CAP
A
A
A
A
A
A
A
A
A
A
A
SS
16
14
12
3
7
6
5
4
2
1
0
Figure 2. 32-Pin SOIC
0
1
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
HSB
DQ
DQ
DQ
DQ
DQ
V
A
W
A
A
A
A
G
A
STK14CA8
E
CC
15
13
8
9
11
10
7
6
5
4
3
[2]
Page 3 of 17
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