CY7C225A-30DMB Cypress Semiconductor Corp, CY7C225A-30DMB Datasheet - Page 3

• Manufacturer Part Number: CY7C225A-30DMB
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C225A-30DMB

• Density: 4Kb
• Organization: 512x8
• Operating Current: 120mA
• Interface Type: Parallel
• Package Type: CDIP
• Operating Temperature Classification: Military
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -55C to 125C
• Pin Count: 24
• Mounting: Through Hole
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-04001 Rev. *C
Capacitance
AC Test Loads and Waveforms
Operating Modes
The CY7C225A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with synchronous (E
enables and CLEAR and PRESET inputs.
Upon power-up, the synchronous enable (E
in the set condition causing the outputs (O
OFF or high-impedance state. Data is read by applying the
memory location to the address inputs (A
LOW to the enable (E
loaded into the master flip-flops of the data register during the
address set-up time. At the next LOW-to-HIGH transition of the
clock (CP), data is transferred to the slave flip-flops, which
drive the output buffers, and the accessed data will appear at
the outputs (O
also LOW.
The outputs may be disabled at any time by switching the
asynchronous enable (E) to a logic HIGH, and may be
returned to the active state by switching the enable to a logic
LOW.
Regardless of the condition of E, the outputs will go to the OFF
or high-impedance state upon the next positive clock edge
after the synchronous enable (E
level. If the synchronous enable pin is switched to a logic LOW,
C
C
OUTPUT
Equivalent to:
IN
OUT
INCLUDING
Parameter
5V
JIG AND
SCOPE
(a) NormalLoad
50 pF
0
OUTPUT
−O
[4]
7
) provided the asynchronous enable (E) is
THÉ VENIN EQUIVALENT
R1 250Ω
S
) input. The stored data is accessed and
Input Capacitance
Output Capacitance
R2
167Ω
S
Description
100Ω
) and asynchronous (E) output
S
) input is switched to a HIGH
OUTPUT
INCLUDING
5V
[4]
JIG AND
0
0
SCOPE
2.0V
S
−O
−A
) flip-flop will be
(b) High Z Load
5pF
8
7
) and a logic
) to be in the
T
V
R1 250Ω
A
CC
= 25°C, f = 1 MHz,
=5.0V
R2
167Ω
Test Conditions
the subsequent positive clock edge will return the output to the
active state if E is LOW. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
LOW-to-HIGH transition of the clock. This unique feature
allows the CY7C225A decoders and sense amplifiers to
access the next location while previously addressed data
remains stable on the outputs.
System timing is simplified in that the on-chip edge-triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C225A has buffered asynchronous CLEAR and
PRESET inputs. Applying a LOW to the PRESET input causes
an immediate load of all ones into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). Applying a LOW to the CLEAR input,
resets the flip-flops to all zeros. The initialize data will appear
at the device outputs after the outputs are enabled by bringing
the asynchronous enable (E) LOW.
When power is applied, the (internal) synchronous enable
flip-flop will be in a state such that the outputs will be in the
high-impedance state. In order to enable the outputs, a clock
must occur and the E
time prior to the clock LOW-to-HIGH transition. The E input
may then be used to enable the outputs.
GND
3.0V
< 5 ns
S
input pin must be LOW at least a set-up
10%
ALL INPUT PULSES
90%
Max.
10
10
CY7C225A
Page 3 of 10
90%
10%
Unit
pF
pF
< 5 ns
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