CY7C276-30JC Cypress Semiconductor Corp, CY7C276-30JC Datasheet - Page 2

• Manufacturer Part Number: CY7C276-30JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C276-30JC

• Density: 256Kb
• Access Time (max): 30ns
• Interface Type: Parallel
• Package Type: PLCC
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Not Compliant

1CY7C276
Features
Cypress Semiconductor Corporation
Document #: 38-04004 Rev. *C
• 0.8-micron CMOS for optimum speed/power
• High speed
• 16-bit-wide words
• Three programmable chip selects
• Programmable output enable
• 44-pin PLCC and 44-pin LCC packages
• 100% reprogrammable in windowed packages
• TTL-compatible I/O
• Capable of withstanding greater than 2001V static
CS
CS
CS
Logic Block Diagram
A
A
A
A
discharge
OE
— 25-ns access time
A
A
A
A
A
A
A
A
A
A
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
2
PROGRAMMABLE
DECODE
CS
16K x 16
ARRAY
•
3901 North First Street
16K x 16 Reprogrammable PROM
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Functional Description
The CY7C276 is a high-performance 16K-word by 16-bit
CMOS PROM. It is available in a 44-pin PLCC and a 44-pin
LCC packages, and is 100% reprogrammable in windowed
packages. The memory cells utilize proven EPROM floating
gate technology and word-wide programming algorithms.
The CY7C276 allows the user to independently program the
polarity of each chip select (CS
decoding of up to eight banks of PROM. The polarity of the
asynchronous output enable pin (OE) is also programmable.
In order to read the CY7C276, all three chip selects must be
active and OE must be asserted. The contents of the memory
location addressed by the address lines (A
available on the output lines (D
the outputs until the address changes or the outputs are
disabled.
•
San Jose
V
D
D
V
D
D
D
CC
D
D
D
D
SS
12
11
10
9
8
7
6
5
4
Pin Configuration
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2
LCC/PLCC/CLCC
•
Top View
CA 95134
15
2
Revised September 22, 2006
−CS
−D
1
44 43 42 41 40
0
). The data will remain on
0
). This provides on-chip
•
13
−A
39
38
37
36
35
34
33
32
31
30
29
408-943-2600
CY7C276
0
) will become
A
A
A
A
A
V
V
A
A
A
A
13
12
11
10
9
SS
SS
8
7
6
5
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