IDT7MMV4101S10BG IDT, Integrated Device Technology Inc, IDT7MMV4101S10BG Datasheet - Page 6

• Manufacturer Part Number: IDT7MMV4101S10BG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT7MMV4101S10BG

• Density: 3Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: SDR
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 295mA
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 119
• Word Size: 24b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Not Compliant

ADDRESS
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the t
5. Transition is measured ±200mV from steady state.
ADDRESS
DATA
IDT7MMV4101
128K x 24 Three Megabit 3.3V CMOS Static RAM
DATA
data to be placed on the bus for the required t
is the specified t
write period.
DATA
OUT
WE
CS
WE
CS
IN
IN
WP
.
t
AS
t
AS
(4)
DW
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse
t
WHZ
(5)
t
AW
t
AW
t
t
WP
WC
t
t
WP
WC
CW
(3)
6
HIGH IMPEDANCE
must be greater than or equal to t
t
DATA
DW
t
DW
DATA
Commercial and Industrial Temperature Ranges
IN
VALID
IN
VALID
t
DH
t
t
WHZ
WR
OW
t
WR
+ t
(5)
(3)
t
DW
DH
to allow the I/O drivers to turn off and
(1, 4)
(1,4,5)
(4)
t
CHZ
4083 drw 07
(5)
4083 drw 06
CW
.
.