LTC5100EUFTR Linear Technology, LTC5100EUFTR Datasheet - Page 46
![no-image](/images/manufacturer_photos/0/3/388/linear_technology_sml.jpg)
LTC5100EUFTR
Manufacturer Part Number
LTC5100EUFTR
Description
Manufacturer
Linear Technology
Type
VCSELr
Datasheet
1.LTC5100EUFTR.pdf
(52 pages)
Specifications of LTC5100EUFTR
Number Of Channels
1
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Table 29. Register: IM_DAC—Modulation Current DAC (I
REGISTER
Table 30. Register: PWR_LIMIT_DAC—Optical Power Limit DAC—Read Only (I
REGISTER
LTC5100
REGISTER DEFI ITIO S
46
.BITFIELD
.Reserved
.Im_dac
.BITFIELD
.Reserved
.pwr_limit_dac
Read Only
15:10
15:7
BIT
BIT
9
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
RESET VALUE
RESET VALUE
U
(BIN)
(BIN)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U
FUNCTION AND VALUES
DAC Setting for the Peak-to-Peak Modulation Current (the Combined MODA and MODB Pin Currents)
Read Access to This DAC is Always Available. Write Access is Only Valid if LPC_en = 0.
FUNCTION AND VALUES
DAC Setting for the Over and Underpower Fault Detection Comparator (Read Only)
This Bit Field Has Different Functions Depending on Apc_en.
Constant Current Control (CCC) Mode (Apc_en = 0): Pwr_limit_dac Has No Function in This Mode.
Its Contents are Undefined.
Automatic Power Control (APC) Mode (Apc_en = 1): Pwr_limit_dac Tracks the Value of the Monitor
Diode Current. The Laser Power Controller Continuously Updates the PWR_LIMIT_DAC with the
Most Recent ADC Reading of Imd. Reading the DAC Will Return the Value of Imd_adc Shifted Right
by Three Bits.
I =
M
Im_dac
1024
2
C Command Code 0x02)
• (Im_
rng
1 9
)•
mA typical
(
2
C Command Code 0x03)
)
sn5100 5100fs