TXN174310850F16 Intel, TXN174310850F16 Datasheet - Page 29

• Manufacturer Part Number: TXN174310850F16
• Manufacturer: Intel

Specifications of TXN174310850F16

• Optical Fiber Type: TX/RX
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Mounting: Screw
• Lead Free Status / RoHS Status: Compliant

Intel
Table 50.
Table 51.
Table 52.
2-Nov-2007
Document Number: 306424-005
®
TXN17431 (0850) Optical Transceiver
PHY_XS Control 2 Register (DID = 4h, Address = c000h) (Sheet 2 of 2)
PHY_XS XAUI PRBS Status Register (DID = 4h, Address = c001h)
PHY_XS Rate Adjust Register (DID = 4h, Address = c002h)
15:10
15:4
5:0
Bit
Bit
Bit
3
2
1
0
9
8
7
6
7
6
5
4
3
2
1
0
Lane 3 lock
Lane 2 lock
Lane 1 lock
Lane 0 lock
Receive path XAUI PLL
lock
Reserved
Receive XGXS reset
Transmit XGXS reset
Reserved
XAUI lane 3 PRBS error
XAUI lane 2 PRBS error
XAUI lane 1 PRBS error
XAUI lane 0 PRBS error
Reserved
XGXS transmit rate
adjust overflow
XGXS transmit rate
adjust underflow
XGXS receive rate
adjust overflow
XGXS receive rate
adjust underflow
Reserved
Functionality
Functionality
Functionality
Intel
®
TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA
–
0 = No error detected
1 = Error detected (cleared on read)
0 = No error detected
1 = Error detected (cleared on read)
0 = No error detected
1 = Error detected (cleared on read)
0 = No error detected
1 = Error detected (cleared on read)
–
1 = Overflow
1 = Underflow
1 = Overflow
1 = Underflow
–
0 = Lane 3 not in lock
1 = Lane 3 in lock
0 = Lane 2 not in lock
1 = Lane 2 in lock
0 = Lane 1 not in lock
1 = Lane 1 in lock
0 = Lane 0 not in lock
1 = Lane 0 in lock
0 = PLL not locked
1 = PLL locked
–
0 = Reset
1 = Not reset (default) not self clearing
0 = Reset
1 = Not reset (default) not self clearing
Description
Description
Description
Access
RO, LH
RO, LH
RO, LH
RO, LH
Access
RO, LH
RO, LH
RO, LH
Access
RO,LH
Datasheet
R/W
R/W
RO
RO
RO
RO
RO
–
–
–
–
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