PLRXPL-VE-SG4-38 JDS UNIPHASE, PLRXPL-VE-SG4-38 Datasheet - Page 7

• Manufacturer Part Number: PLRXPL-VE-SG4-38
• Manufacturer: JDS UNIPHASE

Specifications of PLRXPL-VE-SG4-38

• Optical Fiber Type: TX/RX
• Data Transfer Rate: 4250Mbps
• Operating Temperature Classification: Commercial
• Peak Wavelength: 850nm
• Package Type: SFP
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -20C to 85C
• Mounting: Snap Fit To Panel
• Pin Count: 20
• Lead Free Status / RoHS Status: Compliant

Table 2 Transceiver pin descriptions
Pin Number
Receiver
8
9, 10, 11, 14
12
13
15
7
Transmitter
3
1, 17, 20
2
16
18
19
Module Definition
6, 5, 4
7
Symbol
LOS
VeeR
RD-
RD+
VccR
Rate
TX Disable
VeeT
TX Fault
VccT
TD+
TD-
MOD_DEF(0:2)
Name
Loss of Signal Out (OC)
Receiver Signal Ground
Receiver Negative DATA
Out (PECL)
Receiver Positive DATA
Out (PECL)
Receiver Power Supply
Rate Select (LVTTL)
Transmitter Disable In (LVTTL)
Transmitter Signal Ground
Transmitter Fault Out (OC)
Transmitter Power Supply
Transmitter Positive DATA In
(PECL)
Transmitter Negative DATA In
(PECL)
Module Definition Identifiers
ROHS-COMPLIANT 4.25, 2.125, 1.25, 1.0625 GBPS
850 NM SFP TRANSCEIVER
Description
Sufficient optical signal for potential BER < 1x10
Insufficient optical signal for potential BER < 1x10
This pin is open collector compatible, and should be pulled
up to Host Vcc with a 10 kΩ resistor.
These pins should be connected to signal ground on the host board.
Light on = Logic “0” Output
Receiver DATA output is internally AC coupled and series
terminated with a 50 Ω resistor.
Light on = Logic “1” Output
Receiver DATA output is internally AC coupled and series
terminated with a 50 Ω resistor.
This pin should be connected to a filtered +3.3V power supply
on the host board. See Application schematics on page 5 for
filtering suggestions.
This pin should be connected to the auto-negotiation rate
select function
Logic “1” = 4.25Gbps/2.125Gbps receiver bandwidth optimization
Logic “0” = 2.125Gbps/1.25Gbps receiver bandwidth optimization
and Transmitter Extinction Ratio settings meets the requirements
of 1000Base-SX Ethernet Standards
Logic “1” Input (or no connection) = Laser off
Logic “0” Input = Laser on
This pin is internally pulled up to Vcc
These pins should be connected to signal ground on the host board.
Logic “1” Output = Laser Fault (Laser off before t_fault)
Logic “0” Output = Normal Operation
This pin is open collector compatible, and should be pulled
up to Host Vcc with a 10 kΩ resistor.
This pin should be connected to a filtered +3.3V power supply
on the host board. See Application schematics on page 5 for
filtering suggestions.
Logic “1” Input = Light on
Transmitter DATA inputs are internally AC coupled and
terminated with a differential 100 Ω resistor.
Logic “0” Input = Light on
Transmitter DATA inputs are internally AC coupled and
terminated with a differential 100 Ω resistor.
Serial ID with SFF 8472 Diagnostics (See section 3.1)
Module Definition pins should be pulled up to Host Vcc with
10 kΩ resistors.
T
with a 10 kΩ resistor.
-12
-12
= Logic “1”
= Logic “0”