FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 541
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FW82801BA S L5PN
Manufacturer Part Number
FW82801BA S L5PN
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5PN.pdf
(671 pages)
Specifications of FW82801BA S L5PN
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Not Compliant
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15.1.15
T
15.1.16
15.1.17
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
INT_LN—Interrupt Line Register
SID—Subsystem Identification Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
The SID register, in combination with the Subsystem Vendor ID register make it possible for the
operating environment to distinguish one audio subsystem from the other(s).
This register is implemented as write-once register. Once a value is written to it, the value can be
read back. Any subsequent writes will have no effect.
This register is not affected by the D3
CAP_PTR—Capabilities Pointer Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
This register indicates the offset for the capability pointer.
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
This register indicates which PCI interrupt line is used for the AC’97 module interrupt.
15:0
Bit
Bit
7:0
Bit
7:0
Subsystem ID — R/WO.
Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability pointer offset is
offset 50h
Interrupt Line (INT_LN) — R/W. This data is not used by the Intel
to software the interrupt line that the interrupt pin is connected to.
2E
0000h
No
34h
50h
No
3Ch
00h
No
–
2Fh
HOT
to D0 transition.
AC ’97 Audio Controller Registers (D31:F5)
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
®
ICH5. It is used to communicate
R/WO
16 bits
Core
RO
8 bits
Core
R/W
8 bits
Core
541
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