PSD834F2-15J STMicroelectronics, PSD834F2-15J Datasheet - Page 23

• Manufacturer Part Number: PSD834F2-15J
• Manufacturer: STMicroelectronics

Specifications of PSD834F2-15J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two product terms, allowing flexible
memory mapping.
SRAM Select (RS0) is configured using PSDsoft
Express Configuration.
Sector Select and SRAM Select
Sector Select (FS0-FS7, CSBOOT0-CSBOOT3)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDabel. The following rules apply to the
equations for these signals:
1. Primary Flash memory and secondary Flash
2. Any primary Flash memory sector must not be
3. A secondary Flash memory sector must not be
4. SRAM, I/O, and Peripheral I/O spaces must not
5. A secondary Flash memory sector may overlap
6. SRAM, I/O, and Peripheral I/O spaces may
Example. FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to
87FFh. Any address in the range of RS0 always
memory Sector Select signals must not be
larger than the physical sector size.
mapped in the same memory space as another
Flash memory sector.
mapped in the same memory space as another
secondary Flash memory sector.
overlap.
a primary Flash memory sector. In case of
overlap, priority is given to the secondary Flash
memory sector.
overlap any other memory sector. Priority is
given to the SRAM, I/O, or Peripheral I/O.
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash memory seg-
ment 0. You can see that half of the primary Flash
memory segment 0 and one-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example. Also note that an equation that de-
fined FS1 to anywhere in the range of 8000h to
BFFFh would not be valid.
Figure 6 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not overlap. Level one has the highest priority and
level 3 has the lowest.
Figure 6. Priority Level of Memory and I/O
Components
Highest Priority
Lowest Priority
Primary Flash Memory
Non-Volatile Memory
SRAM, I /O, or
Peripheral I /O
Secondary
Level 1
Level 2
Level 3
PSD834F2V
AI02867D
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