CY7C63231A-PC Cypress Semiconductor Corp, CY7C63231A-PC Datasheet - Page 43

• Manufacturer Part Number: CY7C63231A-PC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63231A-PC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Not Compliant

Note:
Document #: 38-08028 Rev. *B
11. The 200Ω internal resistance at the VREG pin gives a standard USB pull-up using this value. Alternately, a 1.5 kΩ, 5% pull-up from D– to an external 3.3V supply
V
V
V
C
I
R
R
V
R
R
V
V
V
V
V
V
V
V
V
R
LO
DI
CM
SE
OLP
ICR
ICF
HC
ITTL
OL1A
OL1B
OL2
OL3
OH
IN
PU
PD
PS2
UP
XIN
can be used.
Differential Input Sensitivity
Differential Input Common Mode Range
Single Ended Receiver Threshold
Transceiver Capacitance
Hi-Z State Data Line Leakage
External Bus Pull-up resistance (D–)
External Bus Pull-down resistance
Static Output Low
Internal PS/2 Pull-up Resistance
Pull-up Resistance
Input Threshold Voltage, CMOS mode
Input Threshold Voltage, CMOS mode
Input Hysteresis Voltage, CMOS mode
Input Threshold Voltage, TTL mode
Output Low Voltage, high drive mode
Output Low Voltage, medium drive mode
Output Low Voltage, low drive mode
Output High Voltage, strong drive mode
Pull-down resistance, XTALIN pin
General Purpose I/O Interface
PS/2 Interface
Parameter
FOR
FOR
V
14.25
1.274
40%
35%
Min
–10
CC
0.2
0.8
3%
0.8
0.8
50
3
8
–2
15.75
1.326
60%
55%
10%
Max
2.5
2.0
0.4
2.0
0.8
0.4
0.4
0.4
20
10
24
7
Units
V
V
V
kΩ
kΩ
pF
µA
kΩ
kΩ
kΩ
V
V
V
V
V
V
V
V
V
V
CC
CC
CC
|(D+)–(D–)|
Isink = 5 mA, SDATA or SCLK pins
0 V < V
1.3 kΩ ±2% to VREG
15 kΩ ±5% to Gnd
SDATA, SCLK pins, PS/2 Enabled
Low to high edge, Port 0 or 1
High to low edge, Port 0 or 1
High to low edge, Port 0 or 1
Ports 0, 1, and 2
I
I
I
I
Port 0 or 1, I
Internal Clock Mode only
OL1
OL1
OL2
OL3
= 50 mA, Ports 0 or 1
= 25 mA, Ports 0 or 1
= 8 mA, Ports 0 or 1
= 2 mA, Ports 0 or 1
in
<3.3 V (D+ or D– pins)
CY7C63221/31A
enCoRe™ USB
OH
Conditions
= 2 mA
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