RG82852GME Intel, RG82852GME Datasheet - Page 10

• Manufacturer Part Number: RG82852GME
• Manufacturer: Intel

Specifications of RG82852GME

• Lead Free Status / RoHS Status: Not Compliant

3.
Problem:
Implication: System hang may occur during boot-up or resume from S3. No other failures have been identified or
Workaround: Please refer to your Intel representative for BIOS workaround details.
Status:
4.
Problem:
Implication: The issue may cause display corruption or a system hang. With the workaround implemented, Intel has
Workaround: A BIOS workaround is available which disconnects upstream AGP FRAME#-based PCI writes to
Status:
5.
Problem:
Implication: If ECC memory is enabled, data corruption or system hang may result.
Workaround: No workaround available. ECC memory will not be supported when using an AGP graphics device.
Status:
Intel
®
852GME/852PM Specification Update
R
cycle testing
machine colliding with BIOS induced RCOMP cycle.
A3,B3 - Intermittent system hangs during BIOS memory testing when power
Systems may intermittently hang during BIOS memory testing as a result of the internal RCOMP state
reported. Issues are resolved with a BIOS workaround.
There are no plans to fix this erratum in silicon.
A4,B4 - AGP PCI Write to system memory may be corrupted
Display corruption or a system hang may result if an upstream AGP FRAME#-based PCI write crosses a
32-byte aligned boundary. Note that upstream AGP FRAME#-based PCI writes which cross a 32-byte
aligned boundary are expected to be rare.
done extensive validation and expects less than 3% impact on system performance.
system memory at 32-byte aligned boundaries. Please refer to your Intel representative for BIOS
workaround details.
There are no plans to fix this erratum in silicon.
A5,B5 - AGP write failure when ECC memory is enabled.
Memory corruption or system hang may result if an AGP semantic write cycle targets a cache line in the
AGP aperture window at the same time a PCI semantic write cycle from another PCI device is targeting
the same cache line if ECC memory is enabled.
There are no plans to fix this erratum in silicon.
11