LSI53C1000R LSI, LSI53C1000R Datasheet - Page 2

• Manufacturer Part Number: LSI53C1000R
• Manufacturer: LSI

Specifications of LSI53C1000R

• Lead Free Status / RoHS Status: Not Compliant

2
F E A T U R E S
• Pin compatible with LSI53C1020
• No external memory required
• 64-bit, 33/66 MHz PCI interface
• Supports Ultra160 SCSI
• Comprehensive SureLINK
Ultra320 controller
• Functionally identical to
• Theoretical 528 MBps zero
• 64-bit addressing supported
• Compliant with PCI 2.2, PCI
• Double transition clocking for
• CRC
• Domain validation
domain validation
• Basic (Level 1) with
• Enhanced (Level 2) with
• Margined (Level 3) with
LSI53C1000 Ultra160 controller
wait state transfer rate
through Dual Address
Cycle (DAC)
Power Management 1.1
and PC99
160 MBps throughput
inquiry command
read/write buffer
margining of LVD drive
strength and programmable
skew test
LSI53C1000R Ultra160 SCSI Controller
U L T R A 1 6 0 S C S I F E A T U R E S
increasing the interface clock rate.
transmission through enhanced detection of communication errors. CRC
provides extra data protection for marginal cable plants and external
devices. CRC is the best way to ensure data protection during hot plugging.
It uses the same proven CRC algorithm used by FDDI, Ethernet, and Fibre
Channel, and detects all single bit errors, all double bit errors, all odd number
of errors, and all burst errors up to 32 bits long. To provide complete end-
to-end protection of the SCSI I/O, AIP protects all non-data phases, augmenting
the CRC feature of Ultra160.
SCSI bus and automatically tests and adjusts the SCSI transfer rate to optimize
interoperability. The LSI53C1000R exceeds Ultra160 by providing not only
Basic (Level 1) and Enhanced (Level 2) domain validation, but adds Margined
(Level 3) domain validation. This enhancement margins LVD drive strength
and clock signal timing characteristics to identify marginal Ultra160 systems.
H A R D W A R E / S O F T W A R E O V E R V I E W
P C I I n t e r f a c e
2.2, and implements a 64-bit/66 MHz PCI bus. It is backward compatible
with 32-bit/33 MHz buses. Additionally, support for DAC is provided.
Specification Revision 1.1 and PC 99, supporting power states D0, D1, D2,
D3hot and D3cold, power management capabilities registers, and program-
mable values for PCI Subsystem Vendor ID and Subsystem ID. Extended
access cycles (Memory Read Line, Memory Read Multiple, and Memory Write
and Invalidate) are also supported.
S C S I P r o c e s s o r
rates up to 160 MBps on a LVD SCSI bus. Integrated LVDlink
support both LVD and single-ended signals with no external transceivers
required. Fast SCSI, Ultra SCSI, Ultra2 SCSI, and Ultra160 SCSI are all
supported by the LSI53C1000R.
Double transition clocking enables throughput of up to 160 MBps without
Cyclic Redundancy Check (CRC) improves the reliability of SCSI data
SureLINK domain validation technology detects the configuration of the
The host PCI interface complies with PCI Local Bus Specification Revision
The LSI53C1000R complies with PCI Power Management Interface
The LSI53C1000R supports wide Ultra160 SCSI synchronous transfer
™
transceivers