LSISAS1068E LSI, LSISAS1068E Datasheet - Page 12

• Manufacturer Part Number: LSISAS1068E
• Manufacturer: LSI

Specifications of LSISAS1068E

• Lead Free Status / RoHS Status: Not Compliant

SAS Phys
Quad Port DMA Arbiter
Context RAM
Signal Descriptions
PCI Express Signals
PCI Express System Signals
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DB08-000274-03
The SAS phys interface to the physical layer, perform serial-to-parallel
conversion of received data and parallel-to-serial conversion of transmit
data, manage phy reset sequences, and perform 8b/10b encoding.
Each quad port module contains a quad port arbiter that interfaces with
the host interface DMA arbiter and determines bus priority between the
four phys in the quad port for DMA transfers.
The context RAM is a memory that is shared between the host interface
module and the quad port modules. The context RAM holds a portion of
the firmware.
The following subsections provide the signal descriptions for the
LSISAS1068E. A “/” following the signal indicates an active LOW signal.
This section describes the PCI Express signals. Refer to the PCI Express
specification for detailed signal descriptions.
This section describes the PCI Express system signals.
P_REFCLK_P PCI Express Differential Clock
P_REFCLK_N PCI Express Differential Clock
RST/
LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller
October 2006 - Version 2.1
This signal provides half of the PCI Express differential
clock input signal.
This signal provides half of the PCI Express differential
clock input signal.
Reset
Asserting the RST/ signal causes a reset.
Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
Input
Input
Input