LSI53C101033 LSI, LSI53C101033 Datasheet - Page 2

• Manufacturer Part Number: LSI53C101033
• Manufacturer: LSI

Specifications of LSI53C101033

• Lead Free Status / RoHS Status: Not Compliant

2
K E Y F E A T U R E S
• Pin compatible with
• No external memory required
• 64-bit, 33/66 MHz PCI interface
• Supports Ultra160 SCSI
• AIP
• High-performance PCI
• SCSI Interrupt Steering Logic
LSI53C896 controller
• Design board to accommodate
• Op code (software) compatible
• Theoretical 528 MBps (on
• 64-bit addressing supported
• Compliant with PCI 2.2, PCI
• Double transition clocking for
• CRC
• Domain validation
• Covers all non-data, including
multifunction device
• Presents one electrical load
• Two independent wide Ultra160
(SISL) alternate interrupt routing
for RAID applications
either device in the same socket
66 MHz part) zero wait state
transfer rate
through Dual Address Cycle
(DAC)
Power Management 1.1
and PC99
160 MBps throughput on
each channel
command, status and messages
to PCI bus
SCSI channels
LSI53C1010 Ultra160 SCSI Controller
U L T R A 1 6 0 S C S I F E A T U R E S
channel for a total of 320 MBps, without increasing the interface clock rate.
through enhanced detection of communication errors. CRC provides extra
data protection for marginal cable plants and external devices. CRC is the
best way to ensure data protection during hot plugging. It uses the same
proven CRC algorithm used by FDDI, Ethernet, and Fibre Channel, and
detects all single bit errors, all double bit errors, all odd number of errors,
and all burst errors up to 32 bits long. To provide complete end-to-end
protection of the SCSI I/O, AIP protects all non-data phases, augmenting the
CRC feature of Ultra160.
bus and automatically tests and adjusts the SCSI transfer rate to optimize
interoperability. The LSI53C1010 exceeds Ultra160 by providing not only
Basic (Level 1) and Enhanced (Level 2) domain validation, but adds Margined
(Level 3) domain validation. This enhancement margins LVD drive strength
and clock signal timing characteristics to identify marginal Ultra160 systems.
H A R D W A R E / S O F T W A R E O V E R V I E W
P C I I n t e r f a c e
2.2, and implements a 64-bit/66 MHz PCI bus. It is backward compatible
with 32-bit/33 MHz buses. Additionally, support for DAC is provided.
electrical load to the PCI bus. It uses one REQ/-GNT/pair to arbitrate for
PCI bus mastership, and separate interrupt signals are generated for SCSI
Function A and SCSI Function B for maximum performance.
Specification Revision 1.1 and PC 99, supporting power states D0, D1, D2,
D3hot and D3cold, power management capabilities registers, and program-
mable values for PCI Subsystem Vendor ID and Subsystem ID. Extended
access cycles (Memory Read Line, Memory Read Multiple, and Memory
Write and Invalidate) are also supported.
Double transition clocking enables throughput of up to 160 MBps on each
Cyclic Redundancy Check (CRC) improves the reliability of SCSI data transmission
SureLINK domain validation technology detects the configuration of the SCSI
The host PCI interface complies with PCI Local Bus Specification Revision
The LSI53C1010 is a true PCI multifunction device in that it presents one
The LSI53C1010 complies with PCI Power Management Interface