MC33580BAPNA Freescale, MC33580BAPNA Datasheet - Page 23

• Manufacturer Part Number: MC33580BAPNA
• Manufacturer: Freescale

Specifications of MC33580BAPNA

• Switch Type: High Side
• Power Switch Family: MC33580
• Input Voltage: 6 to 27V
• Power Switch On Resistance: 30mOhm
• Number Of Outputs: 4
• Mounting: Surface Mount
• Supply Current: 20mA
• Package Type: Power QFN
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Pin Count: 24
• Lead Free Status / RoHS Status: Compliant

DEVICE REGISTER ADDRESSING
addresses and their impact on device operation.
ADDRESS 00000 — STATUS REGISTER (STATR_S)
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO
data. In addition to the device status, this feature provides the
ability to read the content of the OCR0, OCR1, SOCHLR,
CDTOLR, DICR, UOVR, WDR, and NAR registers. (Refer to
the section entitled
Status Return Data)
ADDRESS 00001— OUTPUT CONTROL REGISTER
(OCR0 )
state of four outputs through the SPI. Incoming message bit
D3 : D0 reflects the desired states of the four high-side
outputs (INx_SPI), respectively. A logic [1] enables the
corresponding output switch and a logic [0] turns it OFF.
ADDRESS 01001— OUTPUT CONTROL REGISTER
(OCR1 )
that will be mirrored on the Current Sense (CSNS) pin. A
logic [1] on message bits D3 : D0 enables the CSNS pin for
outputs HS3 : HS0, respectively. In the event the current
sense is enabled for multiple outputs, the current will be
summed. In the event that bits D3 : D0 are all logic [0], the
output CSNS will be tri-stated. This is useful when several
CSNS pins of several devices share the same A /D converter.
ADDRESS A
HIGH AND LOW REGISTER (SOCHLR_S)
output overcurrent low and high detection levels,
respectively. Each output “s” is independently selected for
configuration based on the state of the D12 : D11 bits
(Table
Table 10. Output Selection
Analog Integrated Circuit Device Data
Freescale Semiconductor
The following section describes the possible register
The STATR register is used to read the device status and
The OCR0 register allows the MCU to control the ON / OFF
Incoming message bits D3 : D0 reflect the desired output
The SOCHLR_s register allows the MCU to configure the
A
10).
1
(D12)
0
0
1
1
1
A
0
010 — SELECT OVERCURRENT
Serial Output Communication (Device
beginning on page 25.)
A
0
(D11)
0
1
0
1
HS_s
HS0
HS1
HS2
HS3
addition to protecting the device, this slow blow fuse
emulation feature can be used to optimize the load
requirements matching system characteristics. Bits D2 : D0
set the overcurrent low detection level to one of eight possible
levels, as shown in
overcurrent high detection level to one of two levels, as
outlined in
ADDRESS A
AND OPEN LOAD REGISTER (CDTOLR)
the amount of time the device will allow an overcurrent low
condition before an output latches OFF. Each output is
independently selected for configuration based on A
which are the state of the D12 : D11 bits (refer to
page 23).
Table 11. Overcurrent Low Detection Levels
Table 12. Overcurrent High Detection Levels
SOCL2_s
*
refer to
*
refer to
“_s” refers to the output, which is selected through bits D12
“_s” refers to the output, which is selected through bits D12
Each output can be configured to different levels. In
The CDTOLR register is used by the MCU to determine
SOCH_s
(D2)
0
0
0
0
1
1
1
1
Table
Table
0
1
*
Table
*
SOCL1_s
(D3)
10, page 23.
10, page 23.
1
(D1)
A
0
0
1
1
0
0
1
1
12, page 23.
0
011 — CURRENT DETECTION TIME
Table
*
Overcurrent High Detection (Amperes)
LOGIC COMMANDS AND REGISTERS
SOCL0_s
11, page 23. Bit D3 sets the
FUNCTIONAL DEVICE OPERATION
(D0)
0
1
0
1
0
1
0
1
*
HS0 to HS3
Detection (Amperes)
100
70
Overcurrent Low
HS0 to HS3
18.2
16.3
14.4
12.5
10.5
8.6
6.7
4.8
Table
1
A
:
:
0
10,
D11;
D11;
33580
,
23