LTC2908CDDB-A1#PBF Linear Technology, LTC2908CDDB-A1#PBF Datasheet - Page 13

• Manufacturer Part Number: LTC2908CDDB-A1#PBF
• Manufacturer: Linear Technology

Specifications of LTC2908CDDB-A1#PBF

• Voltage Supervisor Type: Voltage Monitor
• Number Of Voltage Supervisors: 6
• Operating Supply Voltage (min): 0.5V
• Operating Supply Voltage (max): 6V
• Package Type: DFN
• Operating Temperature Classification: Commercial
• Operating Temp Range: 0C to 70C
• Pin Count: 8
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

APPLICATIONS INFORMATION
RST Output Characteristics
The DC characteristics of the RST pull-up and pull-down
strength are shown in the Typical Performance Character-
istics section. The RST output has a weak internal pull-up
to V
The weak pull-up and strong pull-down arrangement al-
lows this pin to have open-drain behavior while possessing
several other benefi cial characteristics.
The weak pull-up eliminates the need for external pull-up
resistors when the rise time on these pins is not critical.
On the other hand, the open-drain RST behavior allows for
wired-OR connections and can be useful when more than
one signal needs to pull down on the RST line.
As noted in the discussion of power-up and power-down,
the circuits that drive RST are powered by V
condition, V
V
Output Rise and Fall Time Estimation
The following formula estimates the output fall time (90% to
10%) for a particular external load capacitance (C
where R
TYPICAL APPLICATIONS
OL
t
FALL
CC
= 0.15V at RST.
= Max(V1, V2) and a strong pull-down to ground.
≈ 2.2 • R
PD
is the on-resistance of the internal pull-down
CC
of at least 0.5V guarantees a maximum
PD
• C
LOAD
Six Supply Monitor, 5% Tolerance, 12V, 5V, 3.3V, 2.5V, 1.8V, 1V
DC/DC
DC/DC
DC/DC
DC/DC
DC/DC
CC
12V
5V
3.3V
2.5V
1.8V
1.0V
. During fault
V1
0.1μF
C1
LOAD
0.1μF
C2
V2 V3 V4
):
LTC2908-A1
GND
transistor estimated to be typically 40Ω at room tempera-
ture (25°C) and C
the pin. Assuming a 150pF load capacitance, the fall time
is about 13ns.
The rise time on the RST pin is limited by a weak internal
pull-up current source to V
mates the output rise time (10% to 90%) at the RST pin:
where R
tor. Notice that this pull-up transistor is modeled as a
6μA current source in the Block Diagram as a typical
representation.
The on-resistance as a function of the V
voltage (for V
as follows:
At V
capacitance, the rise time is 86μs. A smaller external
pull-up resistor may be used if the output needs to pull
up faster and/or to a higher voltage. For example, the rise
time reduces to 3.3μs for a 150pF load capacitance when
using a 10k pull-up resistor.
2.15M
R1
t
R
V
RISE
ADJ1
CC
PU
100k
R2
= 3.3V, R
=
≈ 2.2 • R
PU
MAX V1,V2
86.6k
R3
is the on-resistance of the pull-up transis-
V
ADJ2
CC
RST
(
6 • 10
100k
R4
> 1V) at room temperature is estimated
PU
PU
LOAD
2908 TA02
is about 260k. Using 150pF for load
• C
SYSTEM
5
)
is the external load capacitance on
LOAD
– 1V
CC
Ω
. The following formula esti-
LTC2908
CC
= Max(V1, V2)
13
2908fc