LH75410N0M100C0 Sharp Electronics, LH75410N0M100C0 Datasheet - Page 47

• Manufacturer Part Number: LH75410N0M100C0
• Manufacturer: Sharp Electronics

Specifications of LH75410N0M100C0

• Lead Free Status / RoHS Status: Not Compliant

System-on-Chip
Reset Generation
EXTERNAL RESETS
ARM7TDMI-S core:
• nPOR sets all internal registers to their default state
• nRESETIN sets all internal registers, except the
microcontroller Test Mode. When nPOR is released,
nRESETIN behaves during Reset as described
previously.
INTERNAL RESETS
• System Reset
• RTC Reset.
• An External Reset (a logic LOW signal on the exter-
• A signal from the internal Watchdog Timer
• A Soft Reset.
AHB Master Priority and Arbitration
AHB masters:
• ARM processor
• DMAC
• LCD Controller.
nent and cannot change.
Data Sheet
1 (Highest)
2
3 (Lowest)
PRIORITY
when asserted. It is used as a Power-On Reset.
JTAG circuitry, to their default state when asserted.
nal nRESETIN or nPOR input pin)
Two external signals generate resets to the
When nPOR is asserted, nRESETIN defines the
There are two types of Internal Resets generated:
System and RTC Resets are asserted by:
The reset latency depends on the PLL lock state.
The LH75400/01/10/11 microcontrollers have three
Each AHB master has a priority level that is perma-
Table 9. Bus Master Priority
Color LCDC (LH75401 and LH75411)
LCDC (LH75400 and LH75410)
DMAC
ARM7TDMI-S Core (Default)
BUS MASTER PRIORITY
Version 1.2
Memory Interface Architecture
following data-path management resources on chip:
• AHB and APB data buses
• 16KB of zero-wait-state TCM SRAM accessible via
• 16KB of internal SRAM accessible via processor,
• A Static Memory Controller (SMC) that controls
• A 4-stream general-purpose DMAC.
memory-mapped. This memory map partition has three
views, based on the setting of the REMAP bits in the
Reset, Clock, and Power Controller (RCPC).
dividing of the segments into sections. The external
memory segment is divided into eight 64MB sections,
of which the first four are used, each having a chip
select associated with it. Access to any of the last four
sections does not result in an external bus access and
does not cause a memory abort. The peripheral regis-
ter segment is divided into 4KB peripheral sections, 21
of which are assigned to peripherals.
0xE0000000 -
0xFFFBFFFF
0xA0000000
0xC0000000
0x00000000
0x20000000
0x40000000
0x60000000
0x80000000
ADDRESS
processor
DMAC, and LCDC
access to external memory
The LH75400/01/10/11 microcontrollers provide the
All external and internal system resources are
The second partitioning of memory space is the
Table 10. Memory Mapping
REMAP = 00
(DEFAULT)
TCM SRAM
Reserved
Reserved
Reserved
Reserved
External
Memory
External
Memory
Internal
SRAM
REMAP = 01 REMAP = 10
TCM SRAM
Reserved
Reserved
Reserved
Reserved
External
Memory
Internal
Internal
SRAM
SRAM
LH75400/01/10/11
TCM SRAM
TCM SRAM
Reserved
Reserved
Reserved
Reserved
External
Memory
Internal
SRAM
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