LH7A404N0F092B3 Sharp Electronics, LH7A404N0F092B3 Datasheet - Page 47

LH7A404N0F092B3

Manufacturer Part Number
LH7A404N0F092B3
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LH7A404N0F092B3

Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Processing Unit
Microprocessor
Operating Supply Voltage (min)
2V
Operating Supply Voltage (typ)
2.1V
Operating Supply Voltage (max)
2.2V
Package Type
LFBGA
Pin Count
324
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant

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32-Bit System-on-Chip
Synchronous Memory Controller Waveforms
chronous Burst Read (page already open). Figure 19
shows the waveform and timing for synchronous mem-
ory to activate a bank and Write.
Product data sheet
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCSx.
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is static LOW.
5. SDCKE is static HIGH.
SDRAMcmd
SBANK[1:0]
Figure 18 shows the waveform and timing for a Syn-
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSWE, and nSCSx.
2. tOVXXX represents tOVRA, tOVCA, tOVSVW, or tOVSC. Refer to the AC timing table.
3. tOHXXX represents tOHRA, tOHCA, tOHSVW, or tOHSC.
SA[13:0],
SDRAMcmd
D[31:0]
SCLK
SA[13:0],
SB[1:0]
D[31:0]
SCLK
SCKE
Figure 19. Synchronous Bank Activate and Write
tOVA
t OVXXX
Figure 18. Synchronous Burst Read
READ
COLUMN
BANK,
t OHXXX
t OVB
tOVC
NXP Semiconductors
tOVA
tOVXXX
ACTIVE
tISD tIHD
DATA n
BANK,
tOHXXX
tOHA
ROW
DATA n + 1
DATA n + 2
DATA n + 3
tOVD
WRITE
COLUMN
DATA
BANK,
tOHD
LH7A400-24
LH7A404
LH7A404-13
47

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