MC9S12XDT512MAA Freescale, MC9S12XDT512MAA Datasheet - Page 522

• Manufacturer Part Number: MC9S12XDT512MAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512MAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 12 Serial Peripheral Interface (S12SPIV4)
12.3.2.3
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
The baud rate divisor equation is as follows:
The baud rate can be calculated with the following equation:
522
SPPR[2:0]
SPR[2:0]
Reset
Field
6–4
2–0
W
R
SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in
mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in
a change of these bits will abort a transmission in progress and force the SPI system into idle state.
Bidirectional
Bidirectional
SPI Baud Rate Register (SPIBR)
0
0
7
Pin Mode
For maximum allowed baud rates, please refer to the SPI Electrical
Specification in the Electricals chapter of this data sheet.
Normal
Normal
= Unimplemented or Reserved
SPPR2
0
6
SPC0
Baud Rate = BusClock / BaudRateDivisor
BaudRateDivisor = (SPPR + 1) 2
0
1
0
1
Figure 12-5. SPI Baud Rate Register (SPIBR)
Table 12-4. Bidirectional Pin Configurations
Table 12-5. SPIBR Field Descriptions
BIDIROE
SPPR1
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
X
0
1
X
0
1
Master Mode of Operation
Slave Mode of Operation
MISO not used by SPI
SPPR0
NOTE
0
4
Slave Out
Master In
Slave I/O
Slave In
Description
MISO
(SPR + 1)
0
0
3
MOSI not used by SPI
SPR2
0
2
Master Out
Master I/O
Master In
Slave In
MOSI
Table
Freescale Semiconductor
SPR1
12-6. In master mode,
Table
0
1
12-6. In master
Eqn. 12-1
Eqn. 12-2
SPR0
0
0