PPC440GP-3FC400C Applied Micro Circuits Corporation, PPC440GP-3FC400C Datasheet - Page 47

• Manufacturer Part Number: PPC440GP-3FC400C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GP-3FC400C

• Family Name: 440GP
• Device Core: PowerPC
• Device Core Size: 32/64Bit
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9/1.95V
• Operating Supply Voltage (min): 1.65/1.7V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: FCBGA
• Lead Free Status / RoHS Status: Not Compliant

Revision 1.11 – August 27, 2010
Signal Functional Description
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ to GND)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to 3.3V) or pull-down (recommended value is 1kΩ to GND)
AppliedMicro Proprietary
DDR SDRAM Interface
BA0:1
BankSel0:3
CAS
ClkEn0:3
DM0:8
DQS0:8
ECC0:7
MemAddr00:12
MemClkOut0
MemClkOut0
MemData00:63
MemVRef1:2
RAS
WE
Ethernet Interface
EMCCD,
EMC1RxErr
EMCCrS,
EMC0CrSDV
EMCMDClk
EMCMDIO
EMCRxD0:3,
EMC0RxD0:1,
EMC1RxD0:1
EMCRxDV,
EMC1CrSDV
EMCRxClk
EMCRxErr,
EMC0RxErr
EMCTxClk,
EMCRefClk
Data Sheet
required
Signal Name
Bank Address supporting up to four internal banks.
Selects up to four external DDR SDRAM banks.
Column Address Strobe.
Clock Enable. One for each bank.
Memory write data byte lane masks. MEMDM8 is the byte lane
mask for the ECC byte lane.
Byte lane data strobe. DQS8 is the data strobe for the ECC byte
lane.
ECC check bits 0:7.
Memory address bus.
Subsystem clock.
Memory data bus.
Memory reference voltage (SV
Row Address Strobe.
Write Enable.
MII: Collision detection
RMII 1: Receive error
MII: Carrier sense
RMII 0: Carrier sense data valid
MII and RMII: Management data clock
MII and RMII: Transfer command and status information between
MII and PHY
MII: Receive data
RMII 0: Receive data
RMII 1: Receive data
MII: Receive data valid
RMII 1: Carrier sense data valid
MII: Receive clock
MII: Receive error
RMII 0: Receive error
MII: Transmit clock
RMII: Reference clock
(Sheet 2 of 7)
Description
REF
440GP – Power PC 440GP Embedded Processor
) input.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Voltage Ref
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
Receiver
Type
Notes
5
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