PPC405GPR-3DB266 Applied Micro Circuits Corporation, PPC405GPR-3DB266 Datasheet - Page 28

• Manufacturer Part Number: PPC405GPR-3DB266
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GPR-3DB266

• Family Name: 405GPr
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 266MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / RoHS Status: Not Compliant

405GPr – Power PC 405GPr Embedded Processor
Signal List
The following table provides a summary of the number of package pins associated with each functional interface
group.
Multiplexed Pins
In the table “Signal Functional Description” on page 30, each external signal is listed along with a description of the
signal function. Some signals are multiplexed on the same pin (ball) so that the pin can be used for different
functions. Multiplexed signals are shown as a default signal with a secondary signal in square brackets (for
example, GPIO1[TS1E]). Active-low signals (for example, RAS) are marked with an overline.
It is expected that in any single application a particular pin will always be programmed to serve the same function.
The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible.
In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller address
pins are used as outputs by the PPC405GPr to broadcast an address to external slave devices when the
PPC405GPr has control of the external bus. When, during the course of normal chip operation, an external master
gains ownership of the external bus, these same pins are used as inputs which are driven by the external master
and received by the EBC in the PPC405GPr. In this example, the pins are also bidirectional, serving as both inputs
and outputs.
Intialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 51). Note that the
use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.
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Pin Summary
External peripheral
Thermal (and Gnd)
Internal peripheral
Total Signal Pins
External master
Total Pins
Interrupts
Reserved
Ethernet
SDRAM
Group
System
JTAG
OV
V
Gnd
PCI
DD
DD
No. of Pins
299
456
60
18
71
96
15
18
32
24
59
36
9
7
5
6
Revision 2.05 – March 24, 2008
Data Sheet
AMCC