MCIMX287CVM4B Freescale, MCIMX287CVM4B Datasheet - Page 34

• Manufacturer Part Number: MCIMX287CVM4B
• Manufacturer: Freescale

Specifications of MCIMX287CVM4B

• Lead Free Status / RoHS Status: Compliant

3.4.4.1
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal
timings.
3.4.4.1.1
The receiver functions correctly up to an ENET0_RX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
ENET0_RX_CLK frequency.
Figure 9
the figure.
1
3.4.4.1.2
The transmitter functions correctly up to an ENET0_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET0_TX_CLK frequency.
34
M1
M2
M3
M4
ENET0_RX_DV, ENET0_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
ENET0_RXD[3:0] (inputs)
ID
ENET0_RX_CLK (input)
shows MII receive signal timings.
ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER to
ENET0_RX_CLK setup
ENET0_RX_CLK to ENET0_RXD[3:0], ENET0_RX_DV,
ENET0_RX_ER hold
ENET0_RX_CLK pulse width high
ENET0_RX_CLK pulse width low
ENET0_RX_DV
ENET0_RX_ER
ENET MII Mode Timing
MII Receive Signal Timing (ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER,
and ENET0_RX_CLK)
MII Transmit Signal Timing (ENET0_TXD[3:0], ENET0_TX_EN,
ENET0_TX_ER, and ENET0_TX_CLK)
i.MX28 Applications Processor Data Sheet for Consumer Products, Rev. 0
Figure 9. MII Receive Signal Timing Diagram
Characteristic
Table 38. MII Receive Signal Timing
M1
Table 38
1
M2
describes the timing parameters (M1–M4) shown in
M3
Min.
35%
35%
5
5
M4
Max.
65%
65%
—
—
Freescale Semiconductor
ENET0_RX_CLK
ENET0_RX_CLK
period
period
Unit
ns
ns