MCIMX351AJQ5C Freescale, MCIMX351AJQ5C Datasheet - Page 47
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MCIMX351AJQ5C
Manufacturer Part Number
MCIMX351AJQ5C
Description
Manufacturer
Freescale
Datasheet
1.MCIMX351AJQ5C.pdf
(148 pages)
Specifications of MCIMX351AJQ5C
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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1
Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see
Table 41
SD10
SD7
SD8
SD9
ID
and
Address hold time
SDRAM access time
Data out hold time
Active to read/write command period
Table
SDR SDRAM CLK parameters are measured from the 50% point—that is,
high is defined as 50% of signal value and low is defined as 50% of signal
value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Table 33. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
42.
i.MX35 Applications Processors for Automotive Products, Rev. 9
1
Table 33
Parameter
indicates SDRAM requirements. All output signals
NOTE
Symbol
tOH
tRC
tAH
tAC
Min.
1.8
1.2
10
—
Max.
6.47
—
—
—
clock
Unit
ns
ns
ns
47
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