MCIMX515DJM8C Freescale, MCIMX515DJM8C Datasheet - Page 56

• Manufacturer Part Number: MCIMX515DJM8C
• Manufacturer: Freescale

Specifications of MCIMX515DJM8C

• Operating Temperature (min): -20C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
1
2
3
4
56
WE16
WE17
WE18
WE19
WE10
WE12
WE13
WE14
WE15
WE20
WE21
WE11
WE5
WE6
WE7
WE8
WE9
t is axi_clk cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum allowed BCLK frequency
is 104 MHz. As a result if BCD = 0, axi_clk must be
BCLK of 66.5 MHz. When the clock branch to WEIM is decreased to 104 MHz, other busses are impacted which are clocked
from this source. See the CCM chapter of the i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM)
for a detailed clock tree description.
BCLK parameters are being measured from the 50% point that is, high is defined as 50% of signal value and low is defined
as 50% as signal value.
For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.
The lower 16 bits of the WEIM bus are limited to 90 MHz.”
ID
4
4
4
4
Clock rise to address
invalid
Clock rise to CSx_B valid -0.5t-1.25
Clock rise to CSx_B
invalid
Clock rise to WE_B Valid -0.5t-1.25
Clock rise to WE_B
Invalid
Clock rise to OE_B Valid
Clock rise to OE_B
Invalid
Clock rise to BEy_B Valid -0.5t-1.25
Clock rise to BEy_B
Invalid
Clock rise to ADV_B
Valid
Clock rise to ADV_B
Invalid
Clock rise to Output Data
Valid
Clock rise to Output Data
Invalid
Input Data setup time to
Clock rise
Input Data hold time from
Clock rise
WAIT_B setup time to
Clock rise
WAIT_B hold time from
Clock rise
Parameter
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Table 53. WEIM Bus Timing Parameters (continued)
-0.5t-1.25
-0.5t-1.25
-0.5t-1.25
0.5t-1.25
0.5t-1.25
0.5t-1.25
0.5t-1.25
0.5t-1.25
0.5t-1.25
0.5t-1.25
Min
2
2
2
2
BCD = 0
-0.5t+1.75
-0.5t+1.75
-0.5t+1.75
-0.5t+1.75
-0.5t+1.75
-0.5t+1.75
0.5t+1.75
0.5t+1.75
0.5t+1.75
0.5t+1.75
0.5t+1.75
0.5t+1.75
Max
≤
—
—
—
—
—
104 MHz. If BCD = 1, then 133 MHz is allowed for axi_clk, resulting in a
2t-1.25
2t-1.25
2t-1.25
-t-1.25
-t-1.25
-t-1.25
-t-1.25
-t-1.25
-t-1.25
t-1.25
t-1.25
t-1.25
t-1.25
Min
4
2
4
2
BCD = 1
2t+1.75
2t+1.75
2t+1.75
-t+1.75
-t+1.75
-t+1.75
-t+1.75
-t+1.75
-t+1.75
t+1.75
t+1.75
t+1.75
t+1.75
Max
—
—
—
—
2t-1.25
2t-1.25
2t-1.25
2t-1.25
2t-1.25
2t-1.25
2t-1.25
-t-1.25
-t-1.25
-t-1.25
-t-1.25
-t-1.25
-t-1.25
Min
—
—
—
—
BCD = 2
1
2t+1.75
2t+1.75
2t+1.75
2t+1.75
2t+1.75
2t+1.75
2t+1.75
-t+1.75
-t+1.75
-t+1.75
-t+1.75
-t+1.75
-t+1.75
Max
—
—
—
—
Freescale Semiconductor
3t-1.25
3t-1.25
3t-1.25
3t-1.25
3t-1.25
3t-1.25
3t-1.25
-t-1.25
-t-1.25
-t-1.25
-t-1.25
-t-1.25
-t-1.25
Min
—
—
—
—
BCD = 3
3t+1.75
3t+1.75
3t+1.75
3t+1.75
3t+1.75
3t+1.75
3t+1.75
-t+1.75
-t+1.75
-t+1.75
-t+1.75
-t+1.75
-t+1.75
Max
—
—
—
—