NPE405H-3BA200C Applied Micro Circuits Corporation, NPE405H-3BA200C Datasheet - Page 65

• Manufacturer Part Number: NPE405H-3BA200C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of NPE405H-3BA200C

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

NPe405H – PowerNP NPe405H Embedded Processor
I/O SPECIFICATIONS(A)—266 MHZ
Table 16. I/O Specifications—266MHz (Sheet 1 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
3. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.
4. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
AMCC Proprietary
Ethernet Interface
EMC0MDClk
EMC0MDIO
EMC0TxD0:3
[EMC0Tx0:1D0:1]
[EMC0Tx0:
EMC0TxEn
[EMC0Tx0En]
[EMC0Sync]
EMC0TxErr[EMC0Tx1En]
[EMC1TxD0][EMC1Tx2D0]
[EMC1TxD1][EMC1Tx2D1]
[EMC1TxD2][EMC1Tx3D0]
[EMC1TxD3][EMC1Tx3D1]
[EMC1TxEn][EMC1Tx2En]
[EMC1TxErr][EMC1Tx3En]
PHY0Col[PHY0Rx1Er]l
PHY0CrS[PHY0CrS0DV]
PHY0RxClk
PHY0RxD0:3
[PHY0Rx0:1D0:1]
[PHY0Rx0:3D]
PHY0RxDV[PHY0CRS1DV]
PHY0RxErr[PHY0Rx0Er]
PHY0TxClk[PHY0RefClk]
[PHY1RxD0][PHY1Rx2D0]
[PHY1RxD1][PHY1Rx2D1]
[PHY1RxD2][PHY1Rx3D0]
[PHY1RxD3][PHY1Rx3D1]
[PHY1Col][PHY1Rx3Er]
[PHY1CrS][PHY1CrS2DV]
[PHY1RxClk]
[PHY1RxDV]
[PHY1CrS3DV]
[PHY1RxErr][PHY1Rx2Er]
[PHY1TxClk]
HDLCEX Interface
HDLCEXRxClk
HDLCEXRxDataA:B
HDLCEXRxFS
command is used by SDRAM. Output times in table are in cycle 1.
model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that
the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
3
Signal
D]
Setup Time
async[1.0]
async[1.0]
(T IS min)
[1.0][1.5]
[1.2][1.8]
[1.1][1.8]
[0.9][1.5]
[1.3][1.9]
[1.0][1.6]
[1.4[2.0]
1.5[1.1]
1.5[1.1]
[1.1]
[1.1]
[1.8]
25.6
24.2
100
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
1.7
n/a
n/a
1.1
n/a
n/a
Input (ns)
Hold Time
async[0.7]
async[0.9]
(T IH min)
[2.6][0.5]
[2.2][0.3]
[2.2][0.3]
[2.5][0.5]
[1.5][0.2]
[1.8][0.5]
[2.4][0.4]
1.2[0.8]
1.2[0.8]
[0.7]
[0.1]
[0.1]
n/a
0.0
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
1.2
n/a
n/a
2.0
n/a
n/a
1.1
0.5
period +10ns
1 OPB clock
Valid Delay
(T OV max)
[10.9][6.1]
[10.9][6.1]
[11.4][6.5]
[12.7][6.2]
[12.7][6.0]
[11.3[6.5]
10.8[5.4]
[5.3]
[4.6]
11.4
[5.2]
[4.6]
n/a
n/a
n/a
n/a
9.0
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Output (ns)
1 OPB clock
Hold Time
(T OH min)
[4.8][2.5]]
[4.8][2.5]
[4.8][2.5]
[4.8][2.5]
[4.8][2.5]
[4.8][2.5]
4.0[2.3]
period
[2.3]
[1.5]
[2.3]
[1.5]
n/a
4.1
4.3
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
(maximum)
Output Current (mA)
I/O H
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
12
12
12
12
12
12
12
12
12
12
12
Revision 1.02 – November 16, 2007
(minimum)
I/O L
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
8
8
8
8
8
8
8
8
8
8
8
EMC0MDClk
Data Sheet
PHYRX
PHYRX
PHYRX
PHYTX
PHYTX
PHYTX
Clock
DS2011
1, async
1, async
1, async
Notes
1
1
1
1
1
1
1
1
1
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