STV9118 STMicroelectronics, STV9118 Datasheet
STV9118
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STV9118 Summary of contents
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... External sawtooth configuration Bus-controlled output voltage Synchronization on hor. frequency with phase selection DESCRIPTION The STV9118 is a monolithic integrated circuit as- sembled in a 32-pin shrink dual-in-line plastic package. This IC controls all the functions related to horizontal and vertical deflection in multimode or multi-frequency computer display monitors. ...
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GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... STV9118 1 - GLOSSARY AC Alternate Current ACK ACKnowledge bit of I AGC Automatic Gain Control COMP COMParator CRT Cathode Ray Tube DC Direct Current EHT Extra High Voltage EW East-West H/W HardWare HOT Horizontal Output Transistor Inter-Integrated Circuit IIC Inter-Integrated Circuit MCU Micro-Controller Unit NAND Negated AND (logic operation) ...
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... H/HVSyn 32 VDyCor 1 VSyn 2 31 SDA HLckVBk 3 30 SCL HOscF 4 29 Vcc HPLL2C BOut GND 6 HGND 7 26 HOut RO 25 XRay 8 HPLL1F 9 24 EWOut HPosF 23 VOut 10 HMoiré VCap HFly 21 VGND 12 RefOut 13 20 VAGCCap BComp 19 VOscF 14 BRegIn 18 VEHTIn 15 BISense HEHTIn 16 17 STV9118 5/46 ...
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... Vertical position S-correction Vertical moiré C-correction VCap VDyCor VOut VEHTIn HPLL2C 5 H-drive HOut 26 buffer Safety XRay 25 processor 28 BOut B+ PLL2 BISense 16 DC/DC converter BRegIn 15 controller B+ ref. BComp 14 HMoiré generator H size Pin cushion EWOut 24 Keystone Top corners Bottom corners STV9118 17 HEHTIn ...
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... XRay X-Ray protection input 26 HOut Horizontal drive Output 27 GND Main GrouND 28 BOut B+ DC/DC converter controller Output 29 Vcc Supply voltage 2 30 SCL I C bus Serial CLock Input 2 31 SDA I C bus Serial DAta input/output 32 VDyCor Vertical Dynamic Correction output Function STV9118 7/46 ...
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... STV9118 5 - QUICK REFERENCE DATA General Package Supply voltage Supply current Application category Means of control/Maximum clock frequency EW drive DC/DC converter controller Adjustable DC level output Horizontal section Frequency range Autosync frequency ratio (can be enlarged in application) Positive/Negative polarity of horizontal sync signal/Automatic adaptation Duty cycle range of the drive signal ...
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... Pin HFly Pin HMoiré I (pin) Pins other than HMoiré ESD susceptibility V ESD (human body model: discharge of 100pF through 1. Storage temperature stg T Junction temperature j Parameter BOut SDA VOscF STV9118 Value Unit Min Max -0.4 13 -0.4 5.5 V BI- -0 RefO -0 ...
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... STV9118 7 - ELECTRICAL PARAMETERS AND OPERATING CONDITIONS The medium (middle) value adjustment register composed of bits D0, D1,...,Dn is the one having Dn at "1" and all other bits at "0". The minimum value is the one with all bits at 0, maximum value is the one with all at "1". ...
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... HPLL2C pin Null asym. correction (7) Null asym. correction (8) output Output driven LOW HDUTY (Sad00): x1111111b x0000000b Soft-start/Soft-stop value HPOS (Sad01): 1111111xb Figure 7 0000000xb STV9118 Value Min. Typ. Max. 1.5 390 100 =820pF 27 28.5 29 122 -150 19.6 1.4 6.0 5.0 2.8 3 ...
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... STV9118 Symbol Parameter Contribution of pin cushion asymmetry t /T correction to phase of H-drive vs. static PCAC H phase (via PLL2), measured in corners Contribution of parallelogram correction phase of H-drive vs. static phase (via ParalC H PLL2), measured in corners Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must always be higher than the free-running frequency ...
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... VO VOCapt 3.2 3.5 3.65 3.8 2.25 3.0 3 2.5 VEHT RefO VOscF pin. Any DC current on this pin will SCOR (Sad09 at x0000000b) and null VOut pin. " is duration of this ramp, see VR STV9118 Units s Hz 185 ppm RefO %/V %/V 13/46 ...
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... STV9118 7 DRIVE SECTION V = 12V 25°C CC amb Symbol Parameter V Output voltage on EW Current sourced by I EWOut put Control voltage range on V HEHT TIn pin DC component of the EW-drive V EW-DC signal on EWOut V Breathing compensation – ---------------------------- - V V EW-DC HEHT Temperature drift of DC compo – ------------------------------------- ...
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... VSIZE (Sad07): x0000000b x1111111b VDC-AMP VPOS VDyCor (Sad08): (33) x0000000b x1111111b Value Min. Typ. Max HOThrfr 0 V 1.75 HEHT VRefO =1 =1 > HOThrfr Value Min. Typ. Max. -1.5 TBD =10k 4 (Sad15h maximum 0.6 1.6 at maximum 0.52 1.92 STV9118 Units %/V %/V %/V %/ Units 15/46 ...
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... STV9118 Note 33: Ratio "A/B"of vertical parabola component voltage Note 34: Unsigned value. Polarity selection by 7.8 - DC/DC CONTROLLER SECTION V = 12V 25°C CC amb Symbol Parameter Ext. resistance applied between R B+FB output and BComp Open loop gain of error amplifier A OLG on input BRegIn Unity gain bandwidth of error am- ...
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... VMOIRE (Sad0Bh): x0000000b x1111111b (40) XRay input (18)(42) Normal operation pin as function of ad- HPOS (Sad01) 0000000xb 1111111xb V . RefO 2 C Bus does not accept any data and the STV9118 Value Min. Typ. Max. HLckVBk TBD H.lock 0.1 Yes Yes 1 0.04 0.1 2 7.65 7 ...
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... STV9118 8 - TYPICAL OUTPUT WAVEFORMS 43 Note ( ) Function Sad Pin Vertical Size 07 VOut Vertical Position 08 VOut S-correction 09 VOut C-correction 0A VOut 18/46 Byte Waveform V x0000000 amp(min) V mid(VOut) V x1111111 amp(max) V mid(VOut) x0000000 V mid(VOut) x1000000 V mid(VOut) V mid(VOut) x1111111 x0000000: V VOamp Null V VOS-cor V x1111111: VOamp Max. 0 ¼T ¾ ...
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... Max. (n-1 0000000x EW-DC(min) 0 ½ 1111111x EW-DC(max) 0 ½ x0000000 EW-DC EW-key V x1111111 EW-key V EW-DC V EW-PCC(min) x0000000 0 ½ EW-PCC(max) x1111111 0 ½ EW-TCor(max) x1111111 0 ½ EW-TCor(min) x0000000 0 ½ EW-TBot(max) x1111111 0 ½ EW-TBot(min) x0000000 0 ½T VR STV9118 Effect on Screen (n+1 V-moiré (n+1 19/46 ...
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... STV9118 Function Sad Pin Parallelogram 12h correction Pin cushion asymmetry 11h correction Vertical dynamic 15h VDyCor correction amplitude Note 43: For any H and V correction component of the waveforms on for corrections of H asymmetry, displayed in the table, weight of the other relevant components is nullified (minimum for parabola, S-correction, medium for keystone, all corner corrections, C-correction, parallelogram, parabola asymmetry correction, written in corresponding registers) ...
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... VPOS (Vertical position SCOR (S-correction CCOR (C-correction VMOIRE (Vertical moiré amplitude PCC (Pin cushion correction KEYST (Keystone correction TCC (Top corner correction BCC (Bottom corner correction HSIZE (Horizontal size PCAC (Pin cushion asymmetry correction STV9118 Reserved Reserved 21/46 ...
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... STV9118 Sad Reserved VDyCorPol 15 0: ” " 1 XRayReset VSyncAuto effect Reset (46) (46) 0: Off 0: Off READ MODE (SLAVE ADDRESS = 8D) XX HLock VLock 0: Locked 0: Locked (45) 1: Not locked 1: Not lock. HDUTY Note 44: With exception of HDutySyncV B+SyncV and Note 45: In Read Mode, the device always outputs data of the status register, regardless of sub address previously selected ...
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... BOHEdge H/HVSyn and the 0: Falling edge 1: Rising edge Sad17/D4,D5,D6,D7 - THM, TVM, TH, Test bits. They must be kept at 0 level by appli- cation S/W. has no effect Read-out flags STV9118 XRayReset 2 C Bus data transfer into reg- XRayReset bit. Also see de- BlankMode HLckVBk VOutEn V on VOut pin (see 7 ...
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... STV9118 (47) SadXX/D0 - VDet Flag indicating Detection of V synchronization pulses on VSyn pin. 0: Not detected 1: Detected (47) SadXX/D1 - HVDet Flag indicating Detection synchroni- zation pulses applied on H/HVSyn sync pulses are detected, the flag is set and latched. Disappearance of the sync signal will not lead to reset of the flag. ...
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... C bus slave address (8D) followed 2 C bus control register map, refer to chap- VSyn input. The se- 2 VSyncSel I C bus bit bus status register (5 flags: 2 VSyncAuto I C bus bit) that also uses the STV9118 2 C bus (Serial SDA (Se- C bus sub bus H/HVSyn 25/46 ...
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... STV9118 Figure 2. Horizontal sync signal Positive T H Negative 10.2.2 - Sync. presence detection flags The sync. signal presence detection flags in the status register (VDet, HVDet, VExtrDet) do not show in real time the presence or absence of the corresponding sync. signal. They are latched soon as a single sync. pulse is detected. In or- Figure 3 ...
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... PLL1 2 (pin & LOCK DETECTOR High CHARGE COMP PUMP Low PLL1Pump REF1 Figure 4 on HPLL1F can be disabled bus bit its upper part, shows the position HPOS . PLL1InhEn 2 V-sync (extracted HPLL1F PLL INHIBITION VCO HPosF HOSC 10 HPOS SHAPER STV9118 through HOscF 4 27/46 ...
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... STV9118 Figure 6. Horizontal oscillator (VCO) schematic diagram (PLL1 filter HPLL1F + 9 - from charge pump 10.3.3 - Voltage controlled oscillator The VCO makes part of both PLL1 and PLL2 loops, being an “output” to PLL1 and “input” to PLL2. It delivers a linear sawtooth. plains its principle of operation. The linears are ob- ...
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... I C bus bit or after re bus flag, to protect external HPosF is used to time out (“t Hoff HDUTY (vice versa at soft-stop). and sub chapter Safety functions bus control. In position “Internal” HMOIRE I C bus control. STV9118 on on HOut pin /T for soft bus bit 29/46 ...
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... STV9118 The behaviour of horizontal moiré opti- mised for different deflection design configurations 2 using HMoiré bus bit. This bit kept at 0 Figure 10. Control of HOut and BOut at start/stop at nominal V V (HPosF) V HBNorm V BOn V Soft start HOn Start Start HOut BOut HOut ...
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... OSC VCap Cap. 22 Discharge Controller VMOIRE (I VOscF VPOS (I V value (and so RefO 2 VMOIRE I C bus control,. Transconductance amplifier Charge current REF 20 VAGCCap Sampling Sampling Capacitance S-correction SCOR (I CCOR CCOR C-correction sawtooth discharge 2 VOB VSIZE ( STV9118 V RefO VEHTIn 18 VOut 23 31/46 ...
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... STV9118 10 DRIVE SECTION The goal of the EW drive section is to provide, on pin EWOut, a waveform which, used by an exter- nal DC-coupled power stage, serves to compen- sate for those geometry errors of the picture that are symmetric versus vertical axis across the mid- dle of the picture. ...
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... V mid(VOut) 2 VOut 23 Top parabola generator Vertical ramp 2 2 Bottom parabola generator 2 VDC-AMP (I VDyCorPol ( PCC TCC (I C) Tracking HEHTIn/HSize 2 BCC ( Tracking KEYST (I C) with Hor Frequency 2 PCAC (I To horizontal dyn. phase control 2 PARAL (I STV9118 C) VDyCor HSize 17 HEHTIn C) EWOut 24 C) 33/46 ...
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... STV9118 Figure 13. EWOut output waveforms V (EWOut) V EW-Key Keystone alone V V (VCap) (VCap 10.6 - DYNAMIC CORRECTION OUTPUT SECTION 10.6.1 - Vertical dynamic correction output VDyCor A parabola at vertical deflection frequency is avail- able on pin VDyCor. Its amplitude is adjustable via 2 VDC-AMP I C bus control and polarity controlled ...
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... The internal reference and so the out bus adjustable by means bus control. BOHEdge Timing of Off-to-On transition (Sad17/ on BOut output D3) don’t care Middle of H-flyback plus t 0 Falling edge of H-drive signal 1 Rising edge of H-drive signal BOut R HBOutEn XRayAlarm STV9118 , which C1 BISense BTrigDel 35/46 ...
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... STV9118 10.8 - MISCELLANEOUS 10.8.1 - Safety functions The safety functions comprise supply voltage monitoring with appropriate actions, soft start and soft stop features on H-drive and B-drive signals on HOut and BOut outputs and X-ray protection. For supply voltage supervision, refer to paragraph Power supply and voltage references ...
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... I C HlockEn H-lock detector R V-sawtooth discharge S V-sync Out :2 R L1=No blank/blank level L2=H-lock/unlock level bit/flag HPosF 10 (timing) SOFT START & STOP Q XRayAlarm B-drive inhibit H-drive inhibit H-drive inhibition (overrule) V-drive inhibition B-drive inhibition HLckVbk L3=L1+L2 Int. signal 3 Pin STV9118 HLock 37/46 ...
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... STV9118 10.8.4 - Composite output HLckVBk The composite output HLckVBk same time, information about lock state of PLL1 and early vertical blanking pulse. As both signals have two logical levels, a four level signal is used to define the combination of the two. Schematic di- agram putting together all safety functions and ...
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... Figure 17. Ground layout recommendations STV9118 STV9118 General Ground 39/46 ...
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... STV9118 11 - INTERNAL SCHEMATICS Figure 18. 5V Pins 1-2 200 H/HVSyn VSyn Figure 19. 12V 13 RefOut HLckVBk l 3 Figure 20. 12V Pin 13 HOSCF Pin 4 40/46 Figure 21. 12V 5 HPLL2C Figure 22. 12V RefOut Figure 23. 12V RefOut RefOut 13 ...
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... Figure 24. HPLL1F 9 Figure 25. RefOut 12V HPosF 10 Figure 26. 12V 5V HMoiré 11 Figure 27. HFly 12 Figure 28. BComp 14 Figure 29. 5V BRegIn STV9118 12V 12V 15 41/46 ...
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... STV9118 Figure 30. 12V BISense 16 Figure 31. 12V 18 VEHTIn 17 HEHTIn Figure 32. 12V Pin 13 VOSCF 19 42/46 Figure 33. 12V VAGCCap 20 Figure 34. 12V 22 VCap Figure 35. 12V VOut 23 ...
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... Figure 36. 12V 24 EWOut 32 VDyCor Figure 37. 12V XRay 25 Figure 38. 12V 26 HOut 28 BOut Figure 39. 30 SCL 31SDA STV9118 43/46 ...
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... STV9118 12 - PACKAGE MECHANICAL DATA 32 PINS - PLASTIC SHRINK 32 1 Dimensions Min. A 3.556 A1 0.508 A2 3.048 B 0.356 B1 0.762 C .203 D 27.43 E 9.906 E1 7.620 2.540 44/ Millimeters Typ. Max. 3.759 5.080 3.556 4.572 0.457 0.584 1.016 1.397 0.254 0.356 27.94 28.45 10.41 11.05 8.890 9.398 1.778 10.16 12 ...
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... DATASHEET August 2003 Document created from version 1.1 of TDA9118. Revision follow-up Version 1.0 STV9118 2 ...
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... STV9118 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectron- ics ...