QG80333M500 S L8CC Intel, QG80333M500 S L8CC Datasheet - Page 21

• Manufacturer Part Number: QG80333M500 S L8CC
• Manufacturer: Intel

Specifications of QG80333M500 S L8CC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

21.
Problem:
Implication:
Workaround:
Status:
22.
Problem:
Implication:
Workaround:
Status:
23.
Problem:
Implication:
Workaround:
Status:
Specification Update
Note: Error status registers are unaffected, and properly maintain their values through reset.
PCI Express* and PCI-X header logs and first-error pointers do not remain
sticky through reset
The PCI Express* and PCI-X header logs and first-error pointers do not maintain their values after
a warm/hot reset. These registers are supposed to be unaffected by a warm/hot reset, but instead,
they are reset to default values. The following registers with “sticky” bits are affected:
Errors detected are logged and escalated properly, but after a warm/hot reset, the header logs and
first error pointers reset to their default values.
No workaround
No
Incorrect default value for PCI Express* Flow Control Protocol Error
Severity bit
The PCI Express* Flow Control Error Severity bit (register offset 10C, bit[13]) is programmed to a
default value of 0, indicating an uncorrectable flow control error is reported as non-fatal. This is in
contradiction with the PCI Express* Specification, Revision 1.0a, which requires a default value
of 1, indicating an uncorrectable flow control error is reported as fatal.
Implications for this erratum depend upon the error response strategy implemented in a specific
system.
This bit can be reprogrammed to match the specified default value when desired. BIOS or firmware
must set register 10Ch bit[13] to 1 for both A- and B-segments. For accessing extended bridge
configuration space from the Intel XScale
“Accessing extended bridge configuration space from the Intel XScale® processor” on page
No
Power State bits in PCI Express* Power Management Status and Control
Register mistakenly accept reserved values
The Power State bits (bits[1:0] of PM_CSR at offset 70h), allow a reserved value of 01b or 10b to
be written. This is contrary to the specification, which originally stated that when software attempts
to write an unsupported reserved state to this field, the data must be discarded and a state change
must not occur.
When a reserved state is written to this field, there is a mismatch between the actual power state of
the part and the state reported in configuration space. In some cases, writing a reserved value to this
field can cause the 80333 to transition to the D0 power state, regardless of the previous power state.
Do not write a reserved value to this bit field.
No
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Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
ADVERR_CTL (offset 118h)
HDR_LOG (offset 11Ch)
PCI-XERRUNC_PTR (offset 138h)
PCI-XHDR_LOG (offset 13Ch)
PCI-XD_LOG (offset 14Ch)
PCI-X_ERRLOGCTL (offset 154h)
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
®
processor, see specification clarification 23,
Intel® 80333 I/O Processor
7.
7.
7.
Non-Core Errata
40.
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