MC9328MX1DVH20 Freescale, MC9328MX1DVH20 Datasheet - Page 68
MC9328MX1DVH20
Manufacturer Part Number
MC9328MX1DVH20
Description
Manufacturer
Freescale
Datasheet
1.MC9328MX1DVH20.pdf
(100 pages)
Specifications of MC9328MX1DVH20
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Functional Description and Application Information
4.10
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the
MMC/SD module (inner system) and the application (user programming).
68
Note:
Symbol
T10
T10
T8
T9
T9
•
•
•
•
•
•
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In
are active low.
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period.
In
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
SCLK to valid LD data
End of HSYN idle2 to VSYN edge
(for non-display region)
End of HSYN idle2 to VSYN edge
(for Display region)
VSYN to OE active (Sharp = 0) when VWAIT2 = 0
VSYN to OE active (Sharp = 1) when VWAIT2 = 0
Multimedia Card/Secure Digital Host Controller
Figure
CMD_DAT Output
46, SCLK is always active.
CMD_DAT Input
Table 27. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Bus Clock
Description
Figure 47. Chip-Select Read Cycle Timing Diagram
5a
Valid Data
MC9328MX1 Technical Data, Rev. 7
4a
3a
3b
6a
Valid Data
Minimum
-3
2
1
1
2
7
1
Corresponding Register Value
2
Valid Data
Valid Data
6b
5b
3
2
1
1
2
Figure
4b
Freescale Semiconductor
46, all 3 signals
Unit
Ts
Ts
Ts
Ts
ns
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