MCIMX351AVM4B Freescale, MCIMX351AVM4B Datasheet
MCIMX351AVM4B
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MCIMX351AVM4B Summary of contents
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... High-speed CD ripping to USB, SD/MMC or HDD for virtual CD changer — Audio processing for hands-free telephony: Bluetooth, AEC/NS, and microphone beam forming — Speech recognition © Freescale Semiconductor, Inc., 2010. All rights reserved. Document Number: MCIMX35SR2AEC Rev. 9, 08/2010 IMX35 Package Information Plastic Package Case 5284 mm, 0 ...
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... Ethernet MAC 10/100 Mbps • 1 USB 2.0 host with ULPI interface or internal full-speed PHY 480 Mbps if external HS PHY is used. • 1 USB 2.0 OTG (up to 480 Mbps) controller with internal high-speed OTG PHY i.MX35 Applications Processors for Automotive Products, Rev Freescale Semiconductor ...
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... SPDIF transceiver • 3 UART (up to 4.0 Mbps each) 1.2 Ordering Information Table 1 provides the ordering information for the i.MX35 processors for automotive applications. 1 Description Part Number i.MX351 MCIMX351AVM4B! i.MX351 MCIMX351AVM5B! i.MX355 MCIMX355AVM4B! i.MX355 MCIMX355AVM5B! i.MX356 MCIMX356AVM4B! i.MX356 MCIMX356AVM5B! i.MX351 MCIMX351AJQ4C i ...
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... Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes — Yes — Yes — Yes — — Freescale Semiconductor Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ...
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... The AP domain is built around an ARM1136JF-S core with 16-Kbyte instruction and data L1 caches, an MMU, a 128-Kbyte L2 cache, a multiported crossbar switch, and advanced debug and trace interfaces. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor NOR LCD Display 1 NAND Camera ...
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... The ARM1136JF-S processor core features are as follows: • Integer unit with integral EmbeddedICE • Eight-stage pipeline i.MX35 Applications Processors for Automotive Products, Rev the nwells, and one that is lower than V DD ® technology (which enables direct execution of Java ™ logic SS Freescale Semiconductor ...
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... ARM interface ASRC Asynchronous SDMA sample rate converter i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Table 3. i.MX35 Core Brief Description Table 4. Digital and Analog Modules 1 Subsystem 1-Wire provides the communication line to a 1-Kbit add-only ARM1136 platform memory. the interface can send or receive 1 bit at a time. ...
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... EPIT is enabled by software capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler to adjust the input clock frequency to the required time setting for the interrupts, and the counter value can be programmed on the fly. Brief Description Freescale Semiconductor ...
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... GPU2D Graphics ARM processing unit 2Dv1 i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor 1 Subsystem Connectivity The enhanced serial audio interface (ESAI) provides a full-duplex peripherals serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other DSPs ...
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... I/O. Connectivity The MLB is designed to interface to an automotive MOST ring. peripherals Clock The OSCAUDIO oscillator provides a stable frequency reference for the PLLs. This oscillator is designed to work in conjunction with an external 24.576-MHz crystal. Brief Description industry-standard, bidirectional suitable for 2 C system is Freescale Semiconductor ...
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... Connectivity The SSI is a full-duplex serial port that allows the processor peripherals connected communicate with a variety of serial protocols, including the Freescale Semiconductor SPI standard and the I 2 sound (I S) bus standard. The SSIs interface to the AUDMUX for flexible audio routing. ...
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... GPIO1_0 or TX1. TX1 ALT1 GPIO1_1 ALT6 Tamper-detect logic is used to issue a security violation. This logic is activated if the tamper-detect input is asserted. Tamper-detect logic is enabled by the bit of IOMUXC_GPRA[2]. After enabling the logic impossible to disable it until the next reset. Brief Description Detailed Description Freescale Semiconductor ...
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... VDD is also known as QVCC. 2 HBM ESD classification level according to the AEC-Q100-002 standard 3 Corner pins max. 750 V i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Table 6. i.MX35 Chip-Level Conditions Characteristics CAUTION Table 7 may cause permanent damage to the Table 7. Absolute Maximum Ratings ...
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... V 1.75 — 3.6 V 1.75 — 3.6 V 3.17 3.3 3.43 V 3.17 3.3 3.43 V 3.17 3.3 3.43 V 3.0 3.3 3.6 V 3.0 3.3 3.6 V 3.0 3.3 3.6 V 1.4 — 1.65 V 1.4 — 1.65 V 3.0 3.6 3 –40 — –40 — 105 C Freescale Semiconductor ...
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... Mhz). Module clocks are gated off (can be configured by CGR register). OSC 24M is ON. OSC audio is off (can be configured) RNGC internal osc is off i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Table 9. Interface Frequency Symbol Min JTAG Table 10. i.MX35 Power Modes ...
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... Applications Processors for Automotive Products, Rev Table 10. i.MX35 Power Modes (continued) QVCC (ARM/L2 Peripheral) Typ. Max 1.1 77 µA mA 820 72 CAUTION OSC24M_VDD MVDD/PVDD OSC_AUDO_VDD Typ. Max. Typ. µ 400 2.2 1.2 2.2 µA mA µA 50 1.7 24 Freescale Semiconductor Max. mA µA 35 ...
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... FUSE_VDD should be connected to ground, except when eFuses are to be programmed.) 5. Wait until PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD, USBPHY1_UPLLVDD, OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD, (FUSEVDD, optional). Power supplies are stable + 100 μs. 6. Deassert the POR signal. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor NOTE 17 ...
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... Power On Reset POR_B is normally connected to a power management integrated circuit (PMIC). The PMIC asserts POR_B while the power supplies are turned on and negates POR_B after the power up sequence is finished. See Figure 2. i.MX35 Applications Processors for Automotive Products, Rev Freescale Semiconductor ...
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... MHz. Common supplies have been bundled according to the i.MX35 power-up sequence requirements. Peak numbers are provided for system designers so that the i.MX35 power supply requirements will be satisfied during startup and transient conditions. Freescale recommends that system current measurements be taken with customer-specific use-cases to reflect normal operating conditions in the end system ...
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... Section 4.3.1, “Powering Up.” Table Table 12. Thermal Resistance Data Condition Single layer board (1s) Four layer board (2s2p) Voltage (V) Max Current (mA) 1.47 400 1.65 20 1.9 90 3.6 62 3.6 60 3.6 25 12. These values were measured Symbol Value Unit R 53 ºC/W eJA R 30 ºC/W eJA Freescale Semiconductor ...
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... Table 13. DDR Pin Drive Strength Mode Current Levels Drive Mode Mobile DDR (1.8 V) SDRAM (1.8 V) SDRAM (3.3 V) DDR2 (1.8 V) i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Condition Single layer board (1s) Four layer board (2s2p) — — Natural convection Normal High 3 ...
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... NVCC –0.3 V — V — 410 — mV 330 0.5 × NVCC — V 0.5 × NVCC — — V — 22 — kΩ — 47 — kΩ — 100 — kΩ — 100 — kΩ — — 4.8 kΩ — — 5.9 kΩ Freescale Semiconductor ...
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... High-Level DC CMOS input voltage Low-Level DC CMOS input voltage Differential receiver VTH+ Differential receiver VTH– Input current (no pull-up/down) Tri-state I/O supply current i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Test Condition Voh — Vol — Ioh — Iol — ...
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... V — — 0.4 V –4.0 — — mA –8.0 –12.0 4.0 — — mA 8.0 12.0 2.0 — 3.6 V –0.3V — 0.8 V μA — — ±1 μA — — ±1 Freescale Semiconductor ...
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... Output pin di/dt (standard drive) Table 16. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode Parameter Duty cycle Output pin slew rate (max. drive) i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor 80% 20% PA1 Table 15 through Table 20 are not applicable for the output open drain [NVCC = 3.0 V– ...
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... V/ns 0.85/1.24 1.26/1.70 1.19/1.71 1.78/2.39 V/ns 0.63/0.95 0.95/1.30 0.80/1.19 1.20/1.60 V/ns 0.43/0.64 0.63/0.87 108 250 mA/ns 113 262 82 197 mA/ns 86 207 52 116 mA/ns 55 121 Max. Typ. Units Rise/Fall — 0.72/0.97 1.2/1.5 V/ns 0.43/0.61 0.72/0.95 0.59/0.81 0.98/1.27 V/ns 0.34/0.50 0.56/0.72 Freescale Semiconductor ...
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... Output pin di/dt (high drive) Output pin di/dt (standard drive) Table 20. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode Parameter Duty cycle i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor [NVCC = 1.65 V–1.95 V] (continued) Min. Symbol Test Condition Rise/Fall tps ...
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... Min. Max. Typ. Rise/Fall Rise/Fall — 133 — 1.35/1.5 2.15/2.19 0.46/054 0.72/0.81 1.12/1.16 65 157 373 70 167 396 Min. Max. NVCC + 0.3 NVCC ÷ 2 – 0.25 –0.3 NVCC ÷ 0.125 Freescale Semiconductor 2 3 Units % MHz V/ns mA/ns Units ...
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... Output pin di/dt (standard drive) Table 25. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive (1.8 V) Parameter Clock frequency 1 Output pin slew rate (max. drive) i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Min. Symbol Test Condition Rise/Fall Fduty — ...
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... Signals and Multiplexing” chapter of the reference manual for more details. i.MX35 Applications Processors for Automotive Products, Rev Min. Symbol Test Condition Rise/Fall didt trfi 1.0 pF 0.07/0.08 tpi 1.0 pF 0.35/1.17 tpi 1.0 pF 1.18/1.99 Max. Typ. Units Rise/Fall 202 435 mA/ns 213 456 0.11/0.12 0.16/0.20 ns 0.63/1.53 1.16/2.04 ns 1.45/2.35 1.97/2.85 ns Freescale Semiconductor ...
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... CS6 SS n [3:0] lag time (CS hold time) CS7 MOSI setup time CS8 MOSI hold time CS9 MISO setup time i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor CS2 CS3 CS3 CS2 CS3 CS2 CS3 CS2 Figure 8. CSPI Slave Mode Timing Diagram Table 26 ...
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... Figure 9. ETM TRACECLK Timing Diagram Min. Max. 5 — 5 — Unit Comments MHz 1 2 Tdck Fmodulation < 50 kHz 50 kHz < Fmodulation 300 Hz Fmodulation > 300 KHz μs — μs — mV Fmodulation < 50 kHz 50 kHz < Fmodulation 300 Hz Fmodulation > 300 KHz lists the timing parameters. Freescale Semiconductor Units ns ns ...
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... The i.MX35 NFC supports normal timing mode, using two flash clock cycles for one access of RE and WE. AC timings are provided as multiplications of the clock cycle and fixed delay. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Frequency dependent Figure 10. Trace Data Timing Diagram Min ...
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... Figure 12. Address Latch Cycle Timing DIagram i.MX35 Applications Processors for Automotive Products, Rev Table 30 lists the timing parameters. NF1 NF3 NF5 NF6 NF7 NF8 NF9 Command NF1 NF3 NF4 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address NF2 NF4 Freescale Semiconductor ...
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... Figure 14. Read Data Latch Cycle Timing DIagram ID Parameter NF1 NFCLE setup time NF2 NFCLE hold time NF3 NFCE setup time NF4 NFCE hold time i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor NF1 NF3 NF10 NF11 NF5 NF6 NF8 NF9 Data to NF NF14 NF15 ...
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... N/A tDHR N/A Table 27, "DPLL Specifications," on page NOTE Example Timing for ≈ NFC Clock 33 MHz Min. Max — 25.5 — 28 — 25 — 180 — 44 — 54.5 — 11 — 9 — 0 — 32. Freescale Semiconductor Unit ...
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... WEIM module, and BCLK Address CSx_B RW_B OE_B EBy_B LBA_B Output Data Input Data DTACK_B i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Table 31 lists the timing parameters. WEIM Output Timing WE2 WE1 ... WE4 WE6 WE8 WE10 WE12 ...
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... BCLK is set to maximum drive. i.MX35 Applications Processors for Automotive Products, Rev Table 31. WEIM Bus Timing Parameters Parameter 3 3 NOTE 1 Min. Max. Unit 14.5 — — — 3 3 — ns (BCLK/2) — 3.01 6.9 — — — — ns 5.4 — ns –3.2 — ns Freescale Semiconductor ...
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... Figure 16. Synchronous Memory Timing Diagram for Read Access—WSC = 1 BCLK Last Valid Address ADDR CS[x] RW LBA OE EB[y] DATA Figure 17. Synchronous Memory Timing Diagram for Write Access— i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Table 31 for specific control parameter settings. WE4 V1 WE6 WE14 WE10 WE12 V1 WE18 WE4 ...
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... WE22, WE23 WE20, WE21 WE20, WE21 V1 V1+2 Halfword Halfword WE18, WE19 WE18, WE19 WSC = 2, SYNC = 1, DOL = 0 Address V1 WE15 WE24, WE25 WE22, WE23 WE17 V1 WE16 WE5 Address V2 WE7 WE11 WE13 V2 V2+2 Halfword Halfword WE5 WE7 WE9 WE13 WE17 V1+4 V1+8 V1+12 Freescale Semiconductor ...
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... CS[x] RW LBA OE WE12 EB[y] Figure 21. Muxed A/D Mode Timing Diagram for Synchronous Read Access— WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7 i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor WE5 Address V1 WE16 Write WE15 WSC = 7, LBA = 1, LBN = 1, LAH = 1 WE5 Address V1 WE14 ...
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... Applications Processors for Automotive Products, Rev Table 32 help to determine timing parameters relative chip select (CS) WE31 Address V1 WE39 WE35 WE37 V1 WE43 MAXDI WE31 Addr. V1 WE32A WE40 WE39 WE35A WE37 WE32 Next Address WE40 WE36 WE38 WE44 D(V1) WE44 WE36 WE38 Freescale Semiconductor ...
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... LBA OE BE[y] DATA Figure 24. Asynchronous Memory Write Access CS[x] ADDR/ M_DATA RW LBA OE BE[y] Figure 25. Asynchronous A/D Mux Write Access i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE31 D(V1) Addr. V1 WE32A WE33 WE40A ...
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... CSA) –3 + (OEA + 3 + (OEA + RLBN + RLBN + RLBA + RLBA + ADH + 1 – ADH + 1 – CSA) CSA) — 3 – (OEN – CSN) 4 — (RBEA – CSA) 5 — 3 – (RBEN – CSN) — (LBA – CSA) — 3 – CSN Freescale Semiconductor Unit ...
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... DATA maximum delay from chip input data to its internal FF. 9 DTACK maximum delay from chip dtack input to its internal FF. Note: All configuration parameters (CSA, CSN, WBEA, WBEN, LBA, LBN, OEN, OEA, RBEA, and RBEN) are in cycle units. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Determination By Synchronous Measured 1 Parameters WE14 – ...
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... COL/BA SD8 SD10 SD9 Data SD4 Note: CKE is high during the read/write cycle. SD5 Parameter SD2 SD3 Symbol Min. Max. tCH 3.4 4.1 tCL 3.4 4.1 tCK 7.0 — tCMS 2.0 — tCMH 1.8 — tAS 2.0 — Freescale Semiconductor Unit ...
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... The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 33 are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Parameter NOTE indicates SDRAM requirements. All output signals Symbol Min. ...
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... SD4 SD5 SD4 SD5 COL/BA SD13 SD14 DATA Symbol Min. Max. tCH 0.45 0.55 tCL 0.45 0.55 tCK 7.0 — tCMS 2.4 — tCMH 1.4 — tAS 2.4 — tAH 1.4 — tDS 2.4 — tDH 1.4 — Freescale Semiconductor Unit ...
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... SD1 SDRAM clock high-level width SD2 SDRAM clock low-level width SD3 SDRAM clock cycle time SD6 Address setup time i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor NOTE SD1 SD11 SD10 Figure 29. SDRAM Refresh Timing Diagram Parameter SD2 SD3 SD10 ...
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... SDCLK CS RAS CAS WE ADDR BA CKE Don’t care Figure 30. SDRAM Self-Refresh Cycle Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev Parameter 1 NOTE SD16 Symbol Min. Max. tAH 1.8 — tRP 1 4 tRC 2 20 SD16 Freescale Semiconductor Unit ns clock clock ...
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... PARAMETER DDR1 SDRAM clock high-level width DDR2 SDRAM clock low-level width DDR3 SDRAM clock cycle time DDR4 CS, RAS, CAS, CKE, WE setup time i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor NOTE Symbol tCKS DDR1 DDR4 DDR3 DDR5 DDR4 DDR5 DDR4 ...
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... SDCLK_B differential slew rate of 2 V/ns. For different values, use the derating table. Table 38. Derating Values for DDR2–400, DDR2–533 i.MX35 Applications Processors for Automotive Products, Rev Symbol 1 t 0.475 0. 0.475 IH NOTE DDR2-400 Unit Min Max — ns — ns — ns Freescale Semiconductor ...
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... DDR22 DQS high level width DDR23 DQS low level width These values are for DQ/DM slew rate of 1 V/ns and DQS slew rate of 1 V/ns. For different values use the derating table. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor DDR22 DDR23 DDR18 DDR17 ...
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... SDCLK_B DDR26 DQS (input) DQ (input) Figure 34. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev Table 39. DDR Single-ended Slew Rate NOTE DDR25 DDR24 DATA DATA DATA DATA DATA DATA DATA DATA Freescale Semiconductor ...
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... SD19 Write cycle DQS falling edge to SDCLK output delay time. SD20 Write cycle DQS falling edge to SDCLK output hold time. 1 Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Symbol t DQSQ ...
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... ESDCTL at the negative edge of SDCLK, and the parameters are measured at maximum memory frequency. i.MX35 Applications Processors for Automotive Products, Rev NOTE SD22 SD21 Data Data Data Data Parameter NOTE Data Data Data Data Symbol Min. Max. Unit tDQSQ — 0.85 tQH 2.3 — tDQSCK — 6.7 Freescale Semiconductor ...
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... FSR input (wl) high before SCKR falling edge 75 FSR input hold time after SCKR falling edge 78 SCKT rising edge to FST out (bl) high 79 SCKT rising edge to FST out (bl) low i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor 1,2 Symbol Expression t SSICC 2 × − 9.0 — ...
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... Freescale Semiconductor Unit ...
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... SCKT (Input/Output) FST (Bit) Out FST (Word) Out Data Out FST (Bit) In FST (Word) In i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor First Bit Figure 37. ESAI Transmitter Timing 83 87 Last Bit 91 59 ...
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... HS: high-speed mode. For a high-speed MMC card, the card clock can reach 52 MHz; SD/SDIO can reach 50 MHz. i.MX35 Applications Processors for Automotive Products, Rev First Bit Figure 38. ESAI Receiver Timing Table 44 lists the eSDHCv2 timing characteristics. The Table 70 72 Last Bit 75 44: Freescale Semiconductor ...
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... In normal-speed mode for MMC card, clock frequency can be any value between 0 and 20 MHz. In high-speed mode, clock frequency can be any value between 0–52 MHz satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor SD4 SD2 SD5 SD3 ...
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... Figure 40. MII Receive Signal Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev Table 45 lists MII receive channel timings. Table 45. MII Receive Signal Timing 1 Characteristic Table Min. Max. Unit 5 — 5 — 35% 65% FEC_RX_CLK period 35% 65% FEC_RX_CLK period 45. M4 Freescale Semiconductor ns ns ...
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... Num Characteristic 1 M9 FEC_CRS to FEC_COL minimum pulse width 1 FEC_COL has the same timing in 10 Mbit 7-wire interface mode. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Table 46 lists MII transmit channel timings. Table 46. MII Transmit Signal Timing 1 Table Table 47 ...
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... FEC_MDC pulse width high M15 FEC_MDC pulse width low i.MX35 Applications Processors for Automotive Products, Rev Table M9 Table 48. MII Transmit Signal Timing Characteristic 47. Table 48 lists MII serial management Min. Max. Units 0 — ns — — — ns 40% 60% FEC_MDC period 40% 60% FEC_MDC period Freescale Semiconductor ...
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... CAN modules available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. Refer to the IOMUX chapter of the MCIMX35 Multimedia Applications Processor Reference Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN, respectively. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor M14 M12 M13 ® ...
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... Freescale Semiconductor START Unit Max. μ s — μ s — μ s — 2 μ s 0.9 μ s — μ s — μ s — — ns μ s — ...
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... LZ0P3714 (CCD) Motorola MC30300 (Python) National Semiconductor LM9618 1 Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only camera suppliers. 2 These sensors have not been validated at the time of publication. 4.9.12.2 Functional Description There are three timing modes supported by the IPU. ...
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... Figure 46. Non-Gated Clock Mode Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev Active Line n+1th frame invalid 1st byte Section 4.9.12.2.2, “Gated Clock Figure n+1th frame invalid 1st byte 1st byte Mode”), 46. All incoming pixel clocks are 1st byte Freescale Semiconductor ...
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... Section 4.9.13.3, “Synchronous Interface to Dual-Port Smart Displays” • Section 4.9.13.4, “Asynchronous Interfaces” • Section 4.9.13.5, “Serial Interfaces, Functional Description” i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor is that of a Motorola sensor. Some other sensors may have slightly Table 51 lists the timing parameters. 1/IP1 IP2 IP3 Figure 47 ...
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... All figure parameters shown are programmable. The timing images correspond to inverse polarity i.MX35 Applications Processors for Automotive Products, Rev LINE 2 LINE 3 LINE LINE n – 1 LINE n m – Freescale Semiconductor ...
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... Table 52. Synchronous Display Interface Timing Parameters—Pixel Level ID Parameter IP5 Display interface clock period IP6 Display pixel clock period IP7 Screen width IP8 HSYNC width i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor IP7 IP9 IP8 Start of frame IP14 Figure 49 Symbol Tdicp Tdicp (DISP3_IF_CLK_CNT_D + 1) × Tdicp Tdpcp (SCREEN_WIDTH + 1) × ...
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... Tsw Tsh Tvsw if V_SYNC_WIDTH_L = 0 than (V_SYNC_WIDTH + 1) × Tdpcp else (V_SYNC_WIDTH + 1) × Tsw BGYP × Tsw Tvbi1 (SCREEN_HEIGHT – BGYP – FH) × Tsw Tvbi2 DISP3_IF_CLK_PER_WR ⋅ Tdicp = T HSP_CLK ----------------------------------------------------------------- - HSP_CLK_PERIOD IP20 IP17 IP18 IP19 Value Units Table 53 lists the timing Freescale Semiconductor ...
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... Sharp HR-TFT panel interface timing, and CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY, REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Symbol Min. Tckl Tdicd – Tdicu – 1.5 ...
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... D1 D2 IP21 1 DISPB_D3_CLK period IP23 IP22 IP25 IP26 Symbol (BGXP – 1) × Tdpcp Tsplr CLS_RISE_DELAY × Tdpcp Tclsr CLS_FALL_DELAY × Tdpcp Tclsf PS_FALL_DELAY × Tdpcp Tpsf PS_RISE_DELAY × Tdpcp Tpsr REV_TOGGLE_DELAY × Tdpcp Trev The timing D320 Value Units Freescale Semiconductor ...
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... At a transition to an even field (of the same frame), they do not coincide. • The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC signal being high. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Section 4.9.13.1.5, “Interface to Active Matrix Figure 53 depicts the 75 ...
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... Odd Field Line and Field Timing - NTSC 623 624 625 1 310 311 312 313 Line and Field Timing - PAL Odd Field 267 268 269 273 Even Field Odd Field 314 315 316 336 Even Field Freescale Semiconductor ...
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... ATI single access mode. Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 55, Figure 56, and Figure DISPB_Dn_WR and DISPB_Dn_RD signals. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor 57. These timing images correspond to active-low DISPB_Dn_CS, Figure 54, 77 ...
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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 54. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev Burst access mode with sampling by CS signal Freescale Semiconductor ...
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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 55. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Burst access mode with sampling by WR/RD signals 79 ...
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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 56. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev Burst access mode with sampling by CS signal Freescale Semiconductor ...
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... Figure 57. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram Display read operation can be performed with wait states when each read access takes display interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Burst access mode with sampling by ENABLE signal 81 ...
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... Applications Processors for Automotive Products, Rev Figure 58 shows the timing of the parallel interface with WRITE OPERATION DISP0_RD_WAIT_ST=00 DISP0_RD_WAIT_ST=01 DISP0_RD_WAIT_ST=10 Figure 62 depict timing of asynchronous parallel interfaces based on Table 55 lists the timing parameters at display access level. All READ OPERATION Freescale Semiconductor ...
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... DISPB_D#_CS DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) DISPB_DATA (Input) DISPB_DATA (Output) Figure 59. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor IP28, IP27 IP35, IP33 IP31, IP29 read point IP37 Read Data IP39 IP46,IP44 IP47 IP45, IP43 ...
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... Figure 60. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev IP28, IP27 IP35, IP33 IP31, IP29 read point IP37 Read Data IP39 IP46,IP44 IP47 IP45, IP43 IP42, IP41 IP36, IP34 IP32, IP30 IP38 IP40 Freescale Semiconductor ...
Page 85
... DISPB_D#_CS DISPB_WR (READ/WRITE) DISPB_DATA (Input) DISPB_DATA (Output) Figure 61. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor IP28, IP27 IP35,IP33 IP31, IP29 read point IP37 Read Data IP39 IP46,IP44 IP47 IP45, IP43 ...
Page 86
... Tdicpr – Tdicdr – 1.5 Tdicpr – Tdicdr IP36, IP34 IP32, IP30 IP38 IP40 1 Typ. Max. 2 Tdicpr + 1.5 3 Tdicpw + 1 – Tdicur Tdicdr – Tdicur + 1.5 Tdicpr – Tdicdr + Tdicur + 1.5 6 – Tdicdw – Tdicuw + 1.5 7 Tdicpw – Tdicdw + Tdicuw + 1.5 — — Freescale Semiconductor Units ...
Page 87
... T cei l --------------------------------------------------------------------- - HSP_CLK 2 HSP_CLK_PERIOD 8 This parameter is a requirement to the display connected to the IPU i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Symbol Min. Tdcsw Tdicuw – 1.5 Tdicuw Tdchw Tdicpw – Tdicdw – 1.5 Tdicpw – Tdicdw Tracc 0 Troh Tdrp – ...
Page 88
... The order of the these bits is programmable. The RW bit can be disabled. The following data can consist of one word whole burst. The interface parameters are controlled by the DI_SER_DISPn_CONF registers ( 2). i.MX35 Applications Processors for Automotive Products, Rev Freescale Semiconductor ...
Page 89
... DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) 1 display IF DISPB_D#_CS clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) Figure 64. 4-Wire Serial Interface Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Preamble Write Preamble Read RW RS Preamble D7 1 display IF clock cycle ...
Page 90
... DISPB_SD_D (Input) DISPB_SER_RS Figure 65. 5-Wire Serial Interface (Type 1) Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev Write 1 display IF clock cycle RW D7 Preamble Read 1 display IF clock cycle RW Preamble D7 1 display IF clock cycle Output data 1 display IF clock cycle Input data Freescale Semiconductor ...
Page 91
... DISPB_SER_RS clock cycle DISPB_D#_CS DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) 1 display IF DISPB_SER_RS clock cycle Figure 66. 5-Wire Serial Interface (Type 2) Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Write 1 display IF clock cycle RW D7 Preamble Read 1 display IF clock cycle RW Preamble D7 1 display IF ...
Page 92
... Tdicur – 1.5 Tdicur IP57, IP55 IP51, IP53 IP59 IP61 1 Typ. Max. 2 Tdicpr + 1.5 3 Tdicpw + 1 – Tdicur Tdicdr – Tdicur + 1.5 Tdicpr – Tdicdr + Tdicur Tdicur + 1.5 6 – Tdicdw – Tdicuw + 1.5 7 Tdicpw – Tdicdw + + Tdicuw Tdicuw + 1.5 — Freescale Semiconductor Units ...
Page 93
... --------------------------------------------------------------------- - HSP_CLK 2 HSP_CLK_PERIOD 8 This parameter is a requirement to the display connected to the IPU. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Symbol Min. Tdchr Tdicpr – Tdicdr – 1.5 Tdicpr – Tdicdr Tdcsw Tdicuw – 1.5 Tdicuw Tdchw Tdicpw – Tdicdw – 1.5 Tdicpw – ...
Page 94
... Memory Stick Host Controller (MSHC) Figure 68, Figure 69, and Figure 70 parameters. MSHC_SCLK tSCLKr i.MX35 Applications Processors for Automotive Products, Rev depict the MSHC timings, and tSCLKc tSCLKwh Figure 68. MSHC_CLK Timing Diagram Table 57 and Table 58 list the timing tSCLKwl tSCLKf Freescale Semiconductor ...
Page 95
... MSHC_SCLK MSHC_BS MSHC_DATA (Output) MSHC_DATA (Intput) Figure 69. Transfer Operation Timing Diagram (Serial) i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor tSCLKc tBSsu tDsu tBSh tDh tDd 95 ...
Page 96
... NOTE Parameter Symbol Cycle tSCLKc H pulse length tSCLKwh L pulse length tSCLKwl Rise time tSCLKr Fall time tSCLKf Setup time tBSsu Hold time tBSh tBSh tDh 1 Standards Unit Min. Max. 50 — — — ns — — — — ns Freescale Semiconductor ...
Page 97
... This section describes the electrical information of the MediaLB Controller module. Table 59. MLB 256/512 Fs Timing Parameters Parameter Symbol 1 MLBCLK operating frequency f MLBCLK rise time t i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Parameter Setup time Hold time Output delay time Symbol Cycle tSCLKc tSCLKwh tSCLKwl ...
Page 98
... Fs PLL unlocked — Note — ns — — ns — ns — mckl — ns Note Units Comment Min: 1024 × 44.0 kHz MHz Typ: 1024 × 48.0 kHz Max: 1024 × 48.1 kHz Max: 1024 × Fs PLL unlocked — ns — — ns PLL unlocked Freescale Semiconductor ...
Page 99
... Table 61. RPP Sequence Delay Comparisons Timing Parameters ID Parameters OW1 Reset time low OW2 Presence detect high OW3 Presence detect low OW4 Reset time high i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Min Typ Max 9.7 10.6 — 9.3 10.2 — — — ...
Page 100
... OW8 OW7 OW9 Figure 74. Read Sequence Timing Diagram Table 63. WR1/RD Timing Parameters Symbol t LOW1 t SLOT t RELEASE Min. Typ. Max. Units 60 100 120 OW5 117 120 Table 63 Min. Typ. Max. Units 117 120 15 — 45 Freescale Semiconductor µs µs lists µs µs µs ...
Page 101
... When bus buffers are used the ata_data bus buffer is bidirectional, and uses the direction control signal ata_buffer_en. When ata_buffer_en is asserted, the bus should drive from host to device. When i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Parameter 1 1 ...
Page 102
... Table 65. ATA Timing Parameters Description UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 Value/ Contributing Factor Peripheral clock frequency 15 ns UDMA0 10 ns UDMA1 7 ns UDMA2, UDMA3 5 ns UDMA4 4 ns UDMA5 5.0 ns 4.6 ns UDMA5 12.0 ns 8.5 ns 8 Transceiver Transceiver Transceiver Cable Cable Cable Cable Cable Freescale Semiconductor 1 ...
Page 103
... T > tsu + thi + tskew3 + tskew4 t0 (min.) = (time_1 + time_2 + time_9) × — i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Table 66 lists the timing parameters for PIO read. Figure 76. PIO Read Timing Diagram Table 66. PIO Read Timing Parameters ...
Page 104
... Applications Processors for Automotive Products, Rev. 9 104 Table 67 lists the timing parameters for PIO write. Figure 77. PIO Write Timing Diagram Table 67. PIO Write Timing Parameters Value Controlling Variable time_1 time_2w time_9 If not met, increase time_2w time_4 time_ax time_1, time_2r, time_9 — — Freescale Semiconductor ...
Page 105
... T – (tsu + tco + 2 × tbuf + 2 × tcable2) tL — i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Figure 79 shows timing for MDMA write. Figure 78. MDMA Read Timing Diagram Figure 79. MDMA Write Timing Diagram Value ...
Page 106
... Figure 80. UDMA-In Transfer Starts Timing Diagram Figure 81. UDMA-In Host Terminates Transfer Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev. 9 106 Value Figure 81 shows timing when the UDMA-in device terminates transfer, and Controlling Variable time_jn — shows timing when the UDMA-in Freescale Semiconductor ...
Page 107
... There is a special timing requirement in the ATA host that requires the internal DIOW to go high three clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2. Make ton and toff large enough to avoid bus contention. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Description Controlling Variable time_ack ...
Page 108
... UDMA-out burst. Figure 83. UDMA-Out Transfer Starts Timing Diagram Figure 84. UDMA-Out Host Terminates Transfer Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev. 9 108 Figure 84 shows timing when the UDMA-out device terminates transfer, and shows timing when the UDMA-out Freescale Semiconductor ...
Page 109
... T) – (tskew1 + tskew2) tcvh tcvh ton = time_on × T – tskew1 — ton toff = time_off × T – tskew1 toff i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Value Controlling Variable time_ack time_env time_dvs time_dvh time_cyc time_cyc — ...
Page 110
... The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external i.MX35 Applications Processors for Automotive Products, Rev. 9 110 Signal Description US16 US16 US17 Parameter US17 Conditions / Min. Max. Unit Reference Signal — 6 — 0 — 9 Freescale Semiconductor ...
Page 111
... Data Inputs Data Outputs Data Outputs Data Outputs Figure 88. Boundary Scan (JTAG) Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Table 73 lists the SJC timing parameters. SJ1 SJ2 VM VIH VIL Figure 87. Test Clock Input Timing Diagram SJ4 Input Data Valid ...
Page 112
... Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid SJ13 Figure 90. TRST Timing Diagram Table 73. SJC Timing Parameters Parameter VIH SJ9 All Frequencies Unit Min. Max. 1 100 — — ns — — — ns — — — — ns — Freescale Semiconductor ...
Page 113
... Transition falling Modulating Rx clock (SRCK) period SRCK high period SRCK low period Modulating Tx clock (STCLK) period STCLK high period STCLK low period i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Parameter Table 74. SPDIF Timing Parameters Symbol — — — — ...
Page 114
... For internal frame sync operations using the external clock, the FS timing will be the same as that of Tx Data (for example, during AC97 mode of operation). i.MX35 Applications Processors for Automotive Products, Rev. 9 114 srckp srckpl srckph Figure 91. SRCK Timing stclkp stclkpl stclkph Figure 92. STCLK Timing NOTE Freescale Semiconductor ...
Page 115
... DAM1_T_FS (bl) (Output) DAM1_T_FS (wl) (Output) DAM1_TXD (Output) DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 93. SSI Transmitter with Internal Clock Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor SS1 SS5 SS4 SS8 SS6 SS10 SS16 SS43 SS42 SS1 ...
Page 116
... Internal Clock Operation Synchronous Internal Clock Operation Min. Max. Unit 81.4 — ns 36.0 — ns — 36.0 — ns — — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — — — 15.0 ns — 15.0 ns — 15.0 ns — 10.0 — — ns — Freescale Semiconductor ...
Page 117
... DAM1_T_CLK (Output) DAM1_T_FS (bl) (Output) DAM1_T_FS (wl) (Output) DAM1_RXD (Input) SS48 DAM1_R_CLK (Output) Figure 94. SSI Receiver with Internal Clock Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Table 76 SS1 SS5 SS4 SS9 SS11 SS20 SS21 SS51 SS47 SS50 SS1 SS5 ...
Page 118
... Applications Processors for Automotive Products, Rev. 9 118 Parameter Internal Clock Operation Oversampling Clock Operation Min. Max. Unit 81.4 — ns 36.0 — ns — 36.0 — ns — — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns 10.0 — — ns 15.04 — — ns — — ns — Freescale Semiconductor ...
Page 119
... DAM1_T_FS (bl) (Input) DAM1_T_FS (wl) (Input) DAM1_TXD (Output) DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 95. SSI Transmitter with External Clock Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Table 77 SS22 SS25 SS26 SS29 SS31 SS37 SS38 SS45 SS44 ...
Page 120
... External Clock Operation Synchronous External Clock Operation Min. Max. Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns –10.0 15.0 ns 10.0 — ns –10.0 15.0 ns 10.0 — ns — 15.0 ns — 15.0 ns — 15.0 ns 10.0 — ns 2.0 — ns — 6.0 ns Freescale Semiconductor ...
Page 121
... Figure 96. SSI Receiver with External Clock Timing Diagram Table 78. SSI Receiver with External Clock Timing Parameters ID SS22 (Tx/Rx) CK clock period SS23 (Tx/Rx) CK clock high period SS24 (Tx/Rx) CK clock rise time i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Table 78 SS22 SS26 SS25 SS30 SS32 SS35 SS41 SS40 ...
Page 122
... Bit 4 Bit 5 Bit 6 Min. Max. Unit 36.0 — ns — 6.0 ns –10.0 15.0 ns 10.0 — ns –10.0 15.0 ns 10.0 — ns — 6.0 ns — 6.0 ns 10.0 — ns 2.0 — ns Possible Parity Bit Next Start STOP Bit 7 Par Bit Bit BIT UA1 UA1 Freescale Semiconductor ...
Page 123
... UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. the transmit timing characteristics. UA3 TXD (output) Start Bit 0 Bit Figure 99. UART IrDA Mode Transmit Timing Diagram i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Symbol t Tbit UA2 Bit 2 Bit 3 Bit 4 Bit 5 Symbol ...
Page 124
... ref_clk ref_clk Table 82 UA6 UA5 UA5 Possible Bit 5 Bit 6 Bit 7 Parity Bit Min. Max. 2 1/F – 1/F + baud_rate baud_rate 1/(16 × baud_rate baud_rate (5/16) × (1/F 1.41 us baud_rate Freescale Semiconductor Units — ) — lists STOP BIT Units — — ...
Page 125
... Receive USB_TXOE_B USB_DAT_VP USB_SE0_VM Figure 102. USB Receive Waveform in DAT_SE0 Bidirectional Mode i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Figure 101 Signal Description Transmit enable, active low Tx data when USB_TXOE_B is low Differential Rx data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low ...
Page 126
... SE0 drive when USB_TXOE_B is low Buffered data on DP when USB_TXOE_B is high Buffered data on DM when USB_TXOE_B is high Differential Rx data when USB_TXOE_B is high US9 US12 Max. Unit Conditions/Reference Signal 51.0 % — Figure 103 and Figure 104 show the US11 US10 Freescale Semiconductor ...
Page 127
... Table 87. Signal Definitions—VP_VM Bidirectional Mode Name Direction USB_TXOE_B USB_DAT_VP Out (Tx) In (Rx) USB_SE0_VM Out (Tx) In (Rx) USB_RCV i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor US15/US17 Signal Signal Name Min. Source Out — Out — Out — Out 49 ...
Page 128
... US26 US28 US29 Signal Name Direction USB_DAT_VP Out USB_SE0_VM Out USB_TXOE_B Out USB_DAT_VP Out USB_SE0_VM Out USB_DAT_VP In USB_SE0_VM In US20 US19 US22 US27 Condition/ Min. Max. Unit Reference Signal — 5 — 5 — 5 49.0 51.0 % — –3.0 +3.0 ns USB_DAT_VP — 3 — 3 Freescale Semiconductor ...
Page 129
... In USB_RCV In Transmit USB_TXOE_B USB_DAT_VP USB_SE0_VM US33 Figure 107. USB Transmit Waveform in VP_VM Unidirectional Mode i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Signal Name Direction USB_DAT_VP In USB_RCV In Figure 107 Signal Description Transmit enable, active low Tx VP data when USB_TXOE_B is low ...
Page 130
... Applications Processors for Automotive Products, Rev. 9 130 US38 US40 US39 US41 Signal Direction Min. Max. Out — Out — Out — Out 49.0 Out –3.0 In — In — In –4.0 In –6.0 Unit Conditions/Reference Signal 51.0 % — +3.0 ns USB_DAT_VP 3 3 +4.0 ns USB_VM1 +2.0 ns USB_VP1 Freescale Semiconductor ...
Page 131
... Package Information and Pinout This section includes the following: • Mechanical package drawing • Pin/contact assignment information i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor 131 ...
Page 132
... MAPBGA Production Package 1568-01, 17 × 17 mm, 0.8 Pitch 5.1 See Figure 109 for the package drawing and dimensions of the production package. Figure 109. Production Package: Mechanical Drawing i.MX35 Applications Processors for Automotive Products, Rev. 9 132 Freescale Semiconductor ...
Page 133
... ATA_CS1 1 ATA_DA0 1 ATA_DA1 1 ATA_DA2 1 ATA_DATA0 1 ATA_DATA1 1 ATA_DATA10 1 ATA_DATA11 1 ATA_DATA12 i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Table 94 show the signal assignment on the i.MX35 ball map for silicon Ball Location A5 D7 F15 ATA_DMACK D14 ATA_DMARQ D15 D13 D12 ATA_RESET_B E11 ...
Page 134
... LD17 V8 LD18 W20 LD19 T20 LD2 P3 LD20 N5 LD21 R1 LD22 Ball Location 1 T14 P13 M11 T11 Y11 U11 V11 K2 J5 M20 N17 L3 M1 D20 1 F20 1 G18 1 H20 1 J18 1 J16 1 J19 1 J17 1 J20 1 K14 1 K19 1 K18 1 K20 1 G17 1 K16 1 K17 1 K15 Freescale Semiconductor ...
Page 135
... NGND_EMI1 NGND_EMI1 NGND_EMI2 NGND_EMI3 NGND_EMI3 NGND_JTAG NGND_LCDC NGND_LCDC NGND_MISC NGND_MISC NGND_MLB NGND_NFC NGND_SDIO NVCC_ATA NVCC_ATA NVCC_ATA NVCC_ATA NVCC_CRM NVCC_CSI i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Ball Location Signal ID P1 LD23 P2 LD3 N2 LD4 M3 LD5 N1 LD6 R2 LD7 T2 LD8 N3 LD9 C4 NVCC_EMI2 ...
Page 136
... TX5_RX0 A9 TXD1 C9 TXD2 B9 USBOTG_OC A8 USBOTG_PWR B8 USBPHY1_DM C8 USBPHY1_DP C16 USBPHY1_RREF A7 USBPHY1_UID B7 USBPHY1_UPLLGND A18 USBPHY1_UPLLVDD C15 USBPHY1_UPLLVDD Ball Location C17 A19 E12 E13 B17 A13 A10 C7 G15 U17 R17 P15 R15 Y7 R16 T16 M16 N19 P19 R19 N18 N14 N15 P17 Freescale Semiconductor ...
Page 137
... VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS 1 Not available for the MCIMX351. i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Ball Location Signal ID A17 USBPHY1_VBUS B16 USBPHY1_VDDA_BIAS C14 USBPHY1_VSSA_BIAS A16 USBPHY2_DM A6 USBPHY2_DP B6 VDD D18 ...
Page 138
... CSI_MCLK U3 CSI_PIXCLK W2 CSI_VSYNC W1 CSPI1_MISO T4 CSPI1_MOSI V5 CSPI1_SCLK U5 CSPI1_SPI_RDY Y4 CSPI1_SS0 W4 CSPI1_SS1 V4 CTS1 Ball Location E14 W10 U9 V12 E16 Y10 T10 V10 T12 L16 F17 E19 B20 C19 E18 F19 V16 T15 W16 V15 U14 Y16 U15 W17 V14 W15 Y15 T14 Freescale Semiconductor ...
Page 139
... DQM2 DQM3 EB0 EB1 ECB EXT_ARMCLK EXTAL_AUDIO EXTAL24M FEC_COL FEC_CRS FEC_MDC FEC_MDIO FEC_RDATA0 FEC_RDATA1 FEC_RDATA2 FEC_RDATA3 FEC_RX_CLK FEC_RX_DV FEC_RX_ERR i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Ball Location Signal ID G5 FEC_TDATA0 A2 FEC_TDATA1 D4 FEC_TDATA2 D2 FEC_TDATA3 E6 FEC_TX_CLK E3 FEC_TX_EN F5 FEC_TX_ERR D1 FSR E2 FST ...
Page 140
... SCKT F11 DQM1 G11 SD1 Ball Location G12 F13 F14 G14 P16 H14 J14 L14 M14 R10 P14 E20 V20 U19 T19 T18 M12 M15 N20 N16 P20 R13 P12 W11 Y9 N13 E15 U10 U18 U1 G1 C20 C17 A19 Freescale Semiconductor ...
Page 141
... SD28 SD29 SD3 SD30 SD31 SD4 SD5 SD6 SD7 SD8 SD9 SDBA0 SDBA1 SDCKE0 CAS i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor Ball Location Signal ID V18 SDCLK Y19 SDCLK_B R14 SD0 U16 SD15 W18 SD23 V17 A23 A15 SDWE ...
Page 142
... VSS N7 VSS R7 VSS F8 VSS R8 VSS F9 VSS F12 NVCC_EMI2 R12 VSS G13 VSS H15 VSS J15 VSS A1 VSS Y1 VSS J8 VSTBY M8 WDOG_RST N8 XTAL_AUDIO J9 XTAL24M Ball Location L9 N9 K10 P10 H11 H12 H13 J13 K13 L13 T17 A20 Y20 T9 Y12 V19 U20 Freescale Semiconductor ...
Page 143
... DATA BUF RES EN _DV RQ 15 F_E ET_ RTS RXD ATA_ ATA_ ATA_ ATA_ 1 1 DATA DATA DATA IOR i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor SD3 SD2 SD2 SDQ SD2 SD1 SDQ SD3 SD2 SD2 SD2 SD2 SD1 SD1 ...
Page 144
... REV PL SYN CDC DA C USB USB PHY I2C1 USB USB PHY PHY 1_VS _DAT PHY PHY 1_UP 1_UP SA 1_UI 1_D LLG LLVD Freescale Semiconductor 20 OSC V _AU DIO_ VDD EXT W AL_ AUDI O VSS Y 20 GND A CS2 LBA LD0 F LD7 G LD10 H ...
Page 145
... Product Documentation All related product documentation for the i.MX35 processor is located at http://www.freescale.com/imx. 7 Revision History Table 95 shows the revision history of this document. Note: There were no revisions of this document between revision 1 and revision 4 or between revision 6 and revision 7. Table 95. i.MX35 Data Sheet Revision History ...
Page 146
... Table 24, “AC Electrical Characteristics of DDR Type IO Pins in to exclude mention of slew rate. and Figure 38, “ESAI Receiver Timing,” Figure 37, “ESAI Transmitter Timing.” 5 and 6. Table 23, “AC Electrical Characteristics of DDR modified Figure 16, “Synchronous through Figure 21, “Muxed A/D Mode Timing modified to remove extraneous Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK i.MX35 Applications Processors for Automotive Products, Rev. 9 Freescale Semiconductor 147 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...