CY7C371I-83JC Cypress Semiconductor Corp, CY7C371I-83JC Datasheet
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CY7C371I-83JC
Specifications of CY7C371I-83JC
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CY7C371I-83JC Summary of contents
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... Like all members of the F in I/O resources. Each macrocell in the device features an associated I/O pin, resulting in 32 I/O pins on the CY7C371i. In addition, there are three dedicated inputs and two input/clock pins. Clock ...
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... I/O pin is used as an input. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the two logic blocks on the CY7C371i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM ...
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... V Design Tools Development software for the CY7C371i is available from Cypress’s Warp™, Warp Professional™, and Warp Enter- prise™ software packages. Please refer to the data sheets on these products for more details. Cypress also actively supports almost all third-party design tools ...
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... Min 2. Max Max. CC Test Conditions V = 5.0V at f=1 MHz 5. MHz CCINT CY7C371i Ambient Temperature CCINT 5V ± 0.25V 5V ± 0.25V or 0°C to +70°C 3.3V ± 0.3V −40°C to +85°C 5V ± 0.5V 5V ± 0.5V or 3.3V ± 0.3V Min. Typ. [4] 2.4 [4,5] [4,5] ...
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... INCLUDING JIG AND (b) SCOPE 3.0V GND 2.08V(COM'L) < 2.13V(MIL) Output Waveform Measurement Level V OH 0. 0.5V measured with 35-pF AC Test Load. EA CY7C371i 44-Lead TQFP 44-Lead PLCC 2 5 Max. 100 170Ω (COM'L) 236Ω (MIL) ALL INPUT PULSES 90% 90% 10% ( Unit nH Unit ...
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... All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 13. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C371i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. ...
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... Document #: 38-03032 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS [12] 7C371i−143 7C371i−110 Min. Max. [8] 8 [8] 10 [1] 14 [8] 8 [8] 10 [1] 14 500 PDL CY7C371i 7C371i−83 7C371i−66 7C371iL−83 7C371iL−66 Min. Max. Min. Max. Min 500 500 500 ...
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... LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Document #: 38-03032 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS t ICS PDL ICOL t ICS t WH CY7C371i t SCS t ICO PDLL Page ...
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... REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS Ordering Information Speed (MHz) Ordering Code 143 CY7C371i−143AC CY7C371i−143JC 110 CY7C371i−110AC CY7C371i−110JC CY7C371i–110AI CY7C371i–110JI Document #: 38-03032 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Package Name Package Type ...
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... CY7C371i−83JI CY7C371iL−83AC CY7C371iL−83JC CY7C371iL−83AI CY7C371iL−83JI 66 CY7C371i−66AC CY7C371i−66JC CY7C371i−66AI CY7C371i−66JI CY7C371iL−66AC CY7C371iL−66JC CY7C371iL−66AI CY7C371iL−66JI Package Diagrams Document #: 38-03032 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Package Name Package Type ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000™ FOR ALL NEW DESIGNS 44-Lead Plastic Leaded Chip Carrier J67 CY7C371i 51-85003-*A Page ...
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... Document History Page Document Title: CY7C371i UltraLogic™ 32-Macrocell Flash CPLD Document Number: 38-03032 REV. ECN NO. Issue Date ** 106377 06/18/01 *A 213375 See ECN Document #: 38-03032 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Orig. of Change SZV Changed from Spec #: 38-00497 to 38-03032 FSG Added note to title page: “ ...