IP-POSPHY/L3 Altera, IP-POSPHY/L3 Datasheet - Page 32
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IP-POSPHY/L3
Manufacturer Part Number
IP-POSPHY/L3
Description
Manufacturer
Altera
Datasheet
1.IP-POSPHYL3.pdf
(62 pages)
Specifications of IP-POSPHY/L3
Lead Free Status / RoHS Status
Not Compliant
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3–4
Figure 3–8. Example Implementation 2
Internal Architecture
POS-PHY Level 2 and 3 Compiler User Guide
Switch
OC48
(Link)
'A' Interface
Figure 3–7. Example Implementation
Figure 3–8 on page 3–4
to an OC-48 switch.
The POS-PHY Level 2 and 3 Compiler comprises the following four MegaCore
functions:
■
■
■
■
POS-PHY level 2 link-layer
POS-PHY level 2 PHY-layer
POS-PHY level 3 link-layer
POS-PHY level 3 PHY-layer
FPGA
MegaCore Function
Interface
Level 3
PHY
User Logic
FPGA
shows the FPGA interfacing multiple POS-PHY level 2 devices
Preliminary
Interfaces
Atlantic
FIFO
FIFO
FIFO
FIFO
MegaCore Function 1
MegaCore Function 1
Level 3 Link
Level 3 Link
Interface
(Source)
Interface
(Sink)
Interface
Interface
Interface
Interface
Level 2
Level 2
Level 2
Level 2
Link
Link
Link
Link
'B' Interface
© November 2009 Altera Corporation
Chapter 3: Functional Description
PHY
PHY
OC48 Framer
PHY Device
PHY Device
PHY Device
PHY Device
Level 2
Level 2
Level 2
Level 2
Internal Architecture
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