PALC22V10D-10DMB Cypress Semiconductor Corp, PALC22V10D-10DMB Datasheet - Page 6

• Manufacturer Part Number: PALC22V10D-10DMB
• Manufacturer: Cypress Semiconductor Corp

Specifications of PALC22V10D-10DMB

• Lead Free Status / RoHS Status: Not Compliant

Commercial Switching Characteristics PALC22V10D
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
t
t
t
t
Notes:
10. The test load of part (a) of AC Test Loads and Waveforms is used for measuring t
11. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to
12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
13. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
15. This parameter is calculated from the clock period at f
16. The registers in the PALC22V10D have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
Parameter
PD
EA
ER
CO
S1
S2
H
P
WH
WL
MAX1
MAX2
MAX3
CF
AW
AR
AP
SPR
PR
7.
8.
9.
Part (a) of AC Test Loads and Waveforms is used for all parameters except t
Loads and Waveforms is used for t
Min. times are tested initially and after any design or process changes that may affect these parameters.
This specification is guaranteed for all device outputs changing state in a given access cycle.
t
the point at which a previous HIGH level has fallen to 0.5 volts below V
Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure
proper operation, the rise in V
EA(+)
only. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
Input to Output
Propagation Delay
Input to Output Enable Delay
Input to Output Disable Delay
Clock to Output Delay
Input or Feedback Set-Up Time
Synchronous Preset Set-Up Time
Input Hold Time
External Clock Period (t
Clock Width HIGH
Clock Width LOW
External Maximum Frequency
(1/(t
Data Path Maximum Frequency
(1/(t
Internal Feedback Maximum
Frequency (1/(t
Register Clock to
Feedback Input
Asynchronous Reset Width
Asynchronous Reset Recovery
Time
Asynchronous Reset to
Registered Output Delay
Synchronous Preset Recovery
Time
Power-Up Reset Time
CO
WH
+ t
+ t
S
WL
))
Description
[12]
))
[6, 13]
CC
CF
EA(+)
[6, 15]
must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied.
[6]
+ t
[6]
[8, 9]
.
S
))
[8, 9]
[6,16]
[6,14]
CO
+ t
[10]
S
[11]
)
MAX
internal (1/f
Min.
100
166
133
10
22V10D-7
3
2
5
6
0
3
3
8
5
6
1
MAX3
Max.
OH
7.5
2.5
12
8
8
5
) as measured (see Note above) minus t
min. or a previous LOW level has risen to 0.5 volts above V
6
ER
and t
EA(-)
Min.
76.9
142
[2, 7]
111
22V10D-10
12
10
EA(+)
3
2
6
7
0
3
3
6
8
1
. The test load of part (c) of AC Test Loads and Waveforms is used for measuring
. Part (b) of AC Test Loads and Waveforms is used for t
Max.
10
10
10
13
7
3
Min.
55.5
83.3
68.9
22V10D-15
10
10
20
15
10
10
3
2
0
6
6
1
S
.
Max.
4.5
15
15
15
20
8
Min.
33.3
35.7
38.5
OL
22V10D-25
15
15
30
13
13
25
25
15
3
2
0
1
max. Please see part (e) of AC
PALC22V10D
Max.
ER
25
25
15
13
25
25
. Part (c) of AC Test
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s