IBIS4-A-6600-C-2 Cypress Semiconductor Corp, IBIS4-A-6600-C-2 Datasheet

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IBIS4-A-6600-C-2

Manufacturer Part Number
IBIS4-A-6600-C-2
Description
Manufacturer
Cypress Semiconductor Corp
Type
CMOSr
Datasheet

Specifications of IBIS4-A-6600-C-2

Sensor Image Color Type
Color
Sensor Image Size Range
>= 480,000Pixels
Sensor Image Size
2210x3002Pixels
Operating Supply Voltage (min)
2.5V
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
3.3V
Operating Temp Range
-30C to 65C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
Features
Applications
Cypress Semiconductor Corporation
Document Number: 001-02366 Rev. *E
2210 (H) x 3002 (V) Active Pixels
3.5 µm X 3.5 µm Square Pixels
1 inch Optical Format
Monochrome or Color Digital Output
Frame Rate:
High Dynamic Range Modes: Double Slope, Non Destructive
Read out (NDR)
Electronic Rolling Shutter
Master Clock: 40 MPS/40 MHz
Limited Supplies: 2.5V and 3.3V
-30°C to +65°C Operational Temperature Range
68-Pin LCC Package
Power Dissipation: 0.19W
Machine vision
Biometry
Document Scanning
5 fps (2210 x 3002)
89 fps (640 x 480)
198 Champion Court
Description
The IBIS4-6600 is a solid-state CMOS image sensor that
integrates complete analog image acquisition, and a digitizer
and digital signal processing system on a single chip. This image
sensor has a resolution of 6.6 MPixel with 2210 x 3002 active
pixels. The image size is fully programmable for user-defined
windows. The pixels are on a 3.5 µm pitch. This sensor is
available in a Monochrome version or Bayer (RGB) patterned
color filter array.
The user programmable row and column start and stop positions
enable windowing down to 2x1 pixel window for digital zoom.
Sub sampling reduces resolution while maintaining the constant
field of view. The analog video output of the pixel array is
processed by an on-chip analog signal pipeline. Double
Sampling (DS) eliminates the fixed pattern noise.
The programmable gain and offset amplifier maps the signal
swing to the ADC input range. A 10-bit ADC converts the analog
data to a 10-bit digital word stream. The sensor uses a three-wire
Serial-Parallel (SPI) interface. It operates with a single 2.5V
power supply and requires only one master clock for operation
up to 40 MHz. It is housed in a 68-pin ceramic LCC package.
This data sheet enables you to develop a camera system, based
on the described timing and interfacing given in the following
sections.
Figure 1. IBIS4-6600 Image Sensor
6.6 MP CMOS Image Sensor
San Jose
IBIS4-6600 CYII4SM6600AB
,
CA 95134-1709
Revised March 17, 2009
408-943-2600
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Related parts for IBIS4-A-6600-C-2

IBIS4-A-6600-C-2 Summary of contents

Page 1

... Document Number: 001-02366 Rev. *E 6.6 MP CMOS Image Sensor Description The IBIS4-6600 is a solid-state CMOS image sensor that integrates complete analog image acquisition, and a digitizer and digital signal processing system on a single chip. This image sensor has a resolution of 6.6 MPixel with 2210 x 3002 active pixels. The image size is fully programmable for user-defined windows. The pixels are on a 3.5 µ ...

Page 2

... Typical value of average dark current of the whole pixel array (at 21°C) Dark current RMS value (at 21°C) Measured at digital output (in the dark) Measured at digital output (in the dark) To the first neighboring pixel To the second neighboring pixel Typical (including ADCs) IBIS4-6600 CYII4SM6600AB Remarks Remarks Spectral Response Curve on page 3 ...

Page 3

... The sensor is light sensitive between 400 and 1000 nm. The peak 25% approximately 650 nm. In view of a fill factor of 35%, the QE is close to 70% between 500 and 700 nm. Document Number: 001-02366 Rev. *E IBIS4-6600 CYII4SM6600AB Figure 2. Spectral Response Curve QE 20% ...

Page 4

... Mpixel/s Two on-chip 10-bit ADCs at 20 Msamples/s are multiplexed to one digital 10-bit output at 40 Msamples/s Nominal 2.5V (some supplies require 3.3V for extended dynamic range) 2.5V Serial-to Parallel Interface (SPI) 68-pins LCC IBIS4-6600 CYII4SM6600AB 20000 25000 Table 7 on page 12) Page [+] Feedback ...

Page 5

... GND. Condition Min V DD –0 GND – =min –100 =min 100 System clock <= 40 MHz 70 to analog circuit). DDA IBIS4-6600 CYII4SM6600AB Value Unit –0 ± 350 °C –30 to +85 °C 85 °C 2000 V Typ Max Unit 2.5 3 +65 °C ...

Page 6

... The start address is uploaded through the serial to parallel interface. Most of the signals for the image core shown in generated on-chip by the sequencer. This sequencer also allows running the sensor in basic modes, not fully autonomous. IBIS4-6600 CYII4SM6600AB addres s & data bus Dig. logic (2) ...

Page 7

... Document Number: 001-02366 Rev. *E IBIS4-6600 CYII4SM6600AB Color Filter Array The IBIS4-6600 can also be processed with a Bayer RGB color pattern. Pixel (0,0) has a green filter and is situated on a green-red row. Green1 and Green2 are separately processed color filters and have a different spectral response. Green1 pixels are located on a blue-green row, and green2 pixels are located on a green-red row ...

Page 8

... Black pixels are implemented as "optical" black pixels. Document Number: 001-02366 Rev. *E Figure 8. Relative Response Graph 600 700 800 wavelength (nm) Figure 9. Floor Plan Pixel Array 2222 2210 IBIS4-6600 CYII4SM6600AB blue green 1 green 2 red 900 1000 Dummy ring of pixels , s urrounding complete pixel array. not read ...

Page 9

... Taking into account a pixel rate of 40 MHz, a full frame rate of a little more than 5 frames/s is obtained. The frame period of the IBIS4-6600 sensor is calculated as: => Frame period = (Nr. Lines * (RBT + pixel period * Nr. Pixels)) In this equation: Nr ...

Page 10

... DAC_raw out rcal _ _ DAC OUT VDDA 50K DAC_fine out 50K rcal GNDA Note that in this figure, “K” represents KΩ. IBIS4-6600 CYII4SM6600AB blackref 10K bus1 200K blackref 10K bus2 200K Page [+] Feedback ...

Page 11

... Analog to Digital Converter The IBIS4-6600 has a two 10-bit flash analog digital converters. The ADCs are electrically separated from the image sensor. The inputs of the ADC must be tied externally to the outputs of the output amplifiers. One ADC samples the even columns and the other samples the odd columns ...

Page 12

... Document Number: 001-02366 Rev. *E IBIS4-6600 CYII4SM6600AB In the X direction, two columns are always addressed at the same moment, because the signals from the odd and even columns must be put simultaneously on the corresponding bus. In the Y direction, the rows are addressed one by one. This 7. The bits can be ...

Page 13

... IBIS4-6600 CYII4SM6600AB Frame time [mS] 5.3 19.1 38.9 63.2 121.2 81.5 76.4 89.9 83.7 Page [+] Feedback ...

Page 14

... Figure 15. Pixel Readout in Various Subsample Modes Mode Mode Mode E Document Number: 001-02366 Rev. *E IBIS4-6600 CYII4SM6600AB Mode Mode D Page [+] Feedback ...

Page 15

... This is to halve the influence of the parasitic RC times of the reset and select lines in the pixel array. This can result in a reduction of the row blanking time. This is the case when FAST_RESET in the SEQUENCER register is set the nondestructive readout modes 1 and 2. Figure 17. Electronic Rolling Shutter Operation Line number Document Number: 001-02366 Rev. *E IBIS4-6600 CYII4SM6600AB Figure Figure 16. Electronic Shutter Reset pointer Reset sequence ...

Page 16

... High Dynamic Range Modes Double Slope Integration The IBIS4-6600 has a feature called double slope integration to increase the optical dynamic range of the sensor. The pixel response can be extended over a larger range of light intensities by using a "dual slope integration" (patents pending). This is obtained by adding charge packets from a long and a short integration time in the pixel during the same exposure time ...

Page 17

... RESET_ALL 1 (0001) 10:0 NROF_PIXELS Document Number: 001-02366 Rev. *E IBIS4-6600 CYII4SM6600AB intermediate samples. Requires multiples readings of each pixel, thus higher data throughput. Requires system level digital calculations. The relative position of the pulses is determined by a number of data bits that are uploaded in internal registers through a Serial to Parallel interface (SPI) ...

Page 18

... DAC_RAW_REG 10 (1010) 7:0 DAC_FINE_REG 11 (1011) 7:0 DAC_DARK_REG Document Number: 001-02366 Rev. *E IBIS4-6600 CYII4SM6600AB Description Number of lines to count (Y direction) Max. 3014 (3002 real + 12 dummy pixels) Default value <11:0>:"101111000110" Integration time Default value <11:0>:"000000000001" Delay of sequencer pulses Default value <7:0>:"00000011" ...

Page 19

... Document Number: 001-02366 Rev. *E IBIS4-6600 CYII4SM6600AB Description Default value <10:0>:"00000000000" normal operation 1 = ADC in standby 0 = multiplexing of two ADC outputs 1 = disable multiplexing if ONE = 0: delay of output with one (EXT_CLK = 0) or half (EXT_CLK = 1) clock cycle if ONE = 1: switch between two ADCs 0 = internal clock (same as clock to X shift register and output amplifier) ...

Page 20

... Document Number: 001-02366 Rev. *E IBIS4-6600 CYII4SM6600AB accurate and suffers from kTC noise, while the SLOW mode (= 1) can only make incremental adjustments and is noise free. Approximately 200 or more "slow" calibrations have the same effect as one " ...

Page 21

... Bits 2:7 of the IMAGE_CORE register define the sub sampling mode in the X-direction (bits 2:4) and in the Y-direction (bits 5:7). The sub sampling modes and corresponding bit setting are given in the section Analog to Digital Converter IBIS4-6600 CYII4SM6600AB Last line, followed by sync of left shift-register T int ...

Page 22

... Bitinvert If BITINVERT = 0, 0000000000 is the conversion of the lowest possible input voltage, otherwise the bits are inverted. IBIS4-6600 CYII4SM6600AB 14). The best setting also depends on the Page [+] Feedback ...

Page 23

... REG_CLOCK These control signals must be generated by the external system with the following time constraints to SYS_CLOCK (rising edge = active edge): ■ TSETUP >7.5 ns ■ THOLD > 7 important that these signals are free of any glitches. IBIS4-6600 CYII4SM6600AB A1 D0 Internal register upload Page [+] Feedback ...

Page 24

... Basic Frame and Line Timing The basic frame and line timing of the IBIS4-6600 sensor is shown in The pulse width of Y_CLOCK must be a minimum of one clock cycle and three clock cycles for Y_START. As long as Y_CLOCK is applied, the sequencer stays in a suspended state. T1 Row blanking time: During this period, the X-sequencer generates the control signals to sample the pixel signal and pixel reset levels, and start the readout of one line ...

Page 25

... Table 12 on page 20) T2: 4 SYS_CLOCK cycles. Figure 25. Pixel Output Timing Multiplexing to One Analog Output Document Number: 001-02366 Rev. *E IBIS4-6600 CYII4SM6600AB Multiplexing to One Analog Output The pixel signal at the OUT1 output becomes valid after five Figure 24). The SYS_CLOCK cycles when the internal X_SYNC (equal to start ...

Page 26

... ADC using one analog output. Internally, the ADC samples on the falling edge of the ADC_CLOCK. T1: The ADC has a pipeline delay of 2 ADC_CLOCK cycles. Figure 27. ADC Timing using One Analog Output Document Number: 001-02366 Rev. *E IBIS4-6600 CYII4SM6600AB Page [+] Feedback ...

Page 27

... Black level code 190 Analog output 2 DAC_RAW register See OUT2. Analog input ADC 2 2 digital part [2.5V GND (&substrate) of digital part 0 GND (&substrate) of analog part IBIS4-6600 CYII4SM6600AB Pin Description with kΩ and DDA with DDA with DDA DDA DDA Page [+] Feedback ...

Page 28

... ADC data output - ADC data output - ADC data output - ADC data output 2.5 Reset voltage [2.5V]. Highest voltage to the chip. 3.3V for extended dynamic range or 'hard reset'. - ADC data output - ADC data output - ADC data output (LSB) IBIS4-6600 CYII4SM6600AB Pin Description Page [+] Feedback ...

Page 29

... GND if not used. - Boundary scan (allows debugging of internal nodes): Bus. Leave floating if not used. 0.74 Biasing of X and Y decoder. Connect to V and decouple to GNDD with C = 100 nF therefore favorable to have separate analog and digital DDA IBIS4-6600 CYII4SM6600AB Pin Description with kΩ DDD Page [+] Feedback ...

Page 30

... Package Information Figure 28. 68 Pin LCC Packaging Outline (001-05458 GLASS 43 44 Document Number: 001-02366 Rev IBIS4-6600 CYII4SM6600AB PART NO. TABLE 001-05458 ** Page [+] Feedback ...

Page 31

... Figure 29. 84 Pin JLCC Packaging Outline (001-05462 GLASS VIEW A Document Number: 001-02366 Rev. *E IBIS4-6600 CYII4SM6600AB JLCC PACKAGING OU 001-05462 ** 001-054 Page [+] Feedback ...

Page 32

... Glass Lid Specifications Monochrome Sensor A D263 glass is used as protection glass lid on top of the IBIS4-6600 monochrome sensors. The refraction index of the D263 glass lid is 1.52. Figure 30 shows the transmission characteristics of the D263 glass. Figure 30. Transmittance Curve of the D263 Cover Glass Lid 100 ...

Page 33

... Hexavalent chromium PBB (Polybrominated biphenyls) PBDE (Polybrominated diphenyl ethers) Pb-Free Soldering IBIS4-A-6600-M2 (serial numbers beyond 3694): This product is successfully tested for Pb-free soldering processes, using a reflow temperature profile with maximum 260°C, minimum 40s at 255°C, and minimum 90s at 217°C. ...

Page 34

... D263 is used as monochrome glass lid (see Other packaging combinations are available upon special request. Note The IBIS4-6600 sensor used only in applications not related to Low Vision Aid Applications. A strict exclusivity agreement prevents Cypress from selling the IBIS4-6600 sensor to customers who intend to use it for the above specified applications. ...

Page 35

... FPW *E 2649816 03/17/2009 PCI/AESA Final data sheet. Changed title from “IBIS4-A-6600 CMOS Image Sensor” to Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. For more infor- mation on Image sensor products, please contact imagesensors@cypress.com. ...

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